Datasheet

SN74GTLPH1612
18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES287D – OCTOBER 1999 REVISED AUGUST 2001
3–73
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
CLK
1D
C1
CLK
B1
OEAB
CEAB
CLKAB
LEAB
LEBA
CLKBA
CEBA
OEBA
A1
CE
CE
1
64
63
2
32
34
33
31
3
62
ERC
28
V
REF
39
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