Datasheet

SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350B – JUNE 2001 – REVISED AUGUST 2001
3–67
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
physical representation
PHY
Node
Module
PHY
Node
Module
STRB
DATA
GTLP21395 Transceiver
1394 Backplane PHY
1394 Link-Layer Controller
Host Microprocessor
Terminators
Backplane Trace
Connectors
VME/FB+/CPCI or
GTLP Transceivers
PHY
Node
Module
R
TT
V
TT
V
TT
R
TT
2B
1B
2A 2Y 1A 1Y
STRB
DATA
64-Bit Data Bus 32- to 64-Bit Address Bus
PRODUCT PREVIEW