Datasheet

GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
1–7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SR Slew rate
The average rate of change (i.e., V/ns) for a waveform that is changing from one defined logic level to
another defined logic level
t
a
Access time
The time interval between the application of a specified input pulse and the availability of valid signals
at an output
t
c
Clock cycle time
Clock cycle time is 1/f
max
t
dis
Disable time (of a 3-state or open-collector output)
The propagation time between the specified reference points on the input and output voltage
waveforms with the output changing from either of the defined active levels (high or low) to the
high-impedance (off) state
NOTE: For 3-state outputs, t
dis
= t
PHZ
or t
PLZ
. Open-collector outputs change only if they are low at
the time of disabling, so t
dis
= t
PLH
.
t
en
Enable time (of a 3-state or open-collector output)
The propagation time between the specified reference points on the input and output voltage
waveforms with the output changing from the high-impedance (off) state to either of the defined active
levels (high or low)
NOTE: In the case of memories, this is the access time from an enable input (e.g., OE). For 3-state
outputs, t
en
= t
PZH
or t
PZL
. Open-collector outputs change only if they are responding to data
that would cause the output to go low, so t
en
= t
PHL
.
t
f
Fall time
The time interval between two reference points (90% and 10%, unless otherwise specified) on a
waveform that is changing from the defined high level to the defined low level
t
h
Hold time
The time interval during which a signal is retained at a specified input terminal after an active transition
occurs at another specified input terminal
NOTES: 1. The hold time is the actual time interval between two signal events and is determined by
the system in which the digital circuit operates. A minimum value is specified that is the
shortest interval for which correct operation of the digital circuit is to be expected.
2. The hold time may have a negative value, in which case, the minimum limit defines the
longest interval (between the release of the signal and the active transition) for which correct
operation of the digital circuit is to be expected.
t
pd
Propagation delay time
The time between the specified reference points on the input and output voltage waveforms with the
output changing from one defined level (high or low) to the other defined level (t
pd
= t
PHL
or t
PLH
)
t
PHL
Propagation delay time, high-to-low level output
The time between the specified reference points on the input and output voltage waveforms with the
output changing from the defined high level to the defined low level
t
PHZ
Disable time (of a 3-state output) from high level
The time interval between the specified reference points on the input and the output voltage waveforms
with the 3-state output changing from the defined high level to the high-impedance (off) state