Datasheet

SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES349B JUNE 2001 REVISED AUGUST 2001
3–50
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
SN74GTLP1395 interface with the TSB14AA1 1394 backplane PHY
D 1A, 1B, and 1Y are used for the PHY data signals.
D 2A, 2B, and 2Y are used for the PHY strobe signals.
D PHY N_OEB_D or OCDOE connects to 1OEAB and 2OEAB, which control the PHY transmit signals.
D 1OEBY and 2OEBY are connected to GND because the transceiver must always be able to receive signals
from the backplane and relay them to the PHY.
D 1T/C and 2T/C are connected to GND for inverted signals.
D V
CC
is nominal 3.3 V.
D BIAS V
CC
is connected to nominal 3.3 V to support live insertion.
D V
REF
is normally 2/3 of V
TT
.
D ERC is normally connected to V
CC
for slow edge-rate operation because frequencies of only 50 MHz (S100)
and 25 MHz (S50) are required.
logical representation
1394
Link-
Layer
Controller
Host
Interface
D0–D1
CTL0–CTL1
LREQ
SCLK
1394
Backplane
Physical-
Layer
Controller
TSB14AA1
3.3-V V
CC
BPdata
BPstrb
Tdata
Rdata
Rstrb
Tstrb
OCDOE
1A
1Y
2A
2Y
GND
2OEBY
2OEAB
1B
2B
SN74GTLP1395
2
2
1 k
TDOE
V
CC
GND 1OEBY
GND
2T/C
1T/C GND
1OEAB
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