Datasheet

SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES349B – JUNE 2001 – REVISED AUGUST 2001
3–40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1OEAB
1T/C
1OEBY
5
2
20
ERC
15
1A
7
1Y
1
V
REF
12
2A
9
2Y
3
1B
16
2B
14
2OEBY
18
2T/C
19
2OEAB
10
Pin numbers shown are for the DGV, DW, and PW packages.
PRODUCT PREVIEW