Datasheet

SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286E – OCTOBER 1999 – REVISED AUGUST 2001
3–35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
physical representation
PHY
Node
Module
PHY
Node
Module
STRB
DATA
GTLP1394 Transceiver
1394 Backplane PHY
1394 Link-Layer Controller
Host Microprocessor
Terminators
Backplane Trace
Connectors
VME/FB+/CPCI or
GTLP Transceivers
PHY
Node
Module
R
TT
V
TT
V
TT
R
TT
B2
B1
A2 Y2 A1 Y1
STRB
DATA
64-Bit Data Bus 32- to 64-Bit Address Bus