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GTL/GTLP Logic

High-Performance Backplane Drivers

Data Book

Printed on Recycled Paper

Summary of content (821 pages)

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GTL/GTLP Logic High-Performance Backplane Drivers Data Book Printed on Recycled Paper
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
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INTRODUCTION Texas Instruments provides an array of advanced bus-interface devices. Designers can select the best solutions for speed, level translation, power consumption, noise rejection, fault tolerance, or simply driving a high-speed local bus or backplane. Gunning Transceiver Logic (GTL) devices are reduced-voltage-swing, high-speed interface devices between cards operating at LVTTL logic levels and backplanes operating at GTL signal levels.
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GTL FAMILY SUMMARY Primary features of the GTL devices: • • • 3.3-V or 3.3/5-V VCC operation with 5-V tolerant LVTTL inputs and outputs (I/Os) (except GTL1655), which allows the devices to act as 5-V TTL-to-GTL/GTL+, as well as 3.3-V LVTTL-to-GTL/GTL+, translators. GTL1655 supports live insertion with backplane precharge circuitry. High point-to-point frequencies with acceptable short-backplane frequencies.
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GTLP FAMILY SUMMARY Primary features of the GTLP devices: • • • • • • • • 3.3-V VCC operation with 5-V tolerant LVTTL I/Os, which allows the devices to act as 5-V TTL-to-GTL/GTL+, as well as 3.3-V LVTTL-to-GTL/GTL+, translators. Optimized OEC circuitry allows clock frequencies of >80 MHz in high-performance, heavily loaded backplane applications.
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GTLP FAMILY SUMMARY (CONTINUED) Additional features of GTLP devices: • • • • • • • • viii Ioff circuitry prevents damage to the device during partial power down, a feature of all GTLP devices (see Ioff in the data sheets). PU3S forces outputs to the high-impedance state during power up and power down, which prevents driver conflict during hot swap or hot insertion, a feature of all GTLP devices (see IOZPU and IOZPD in the data sheets).
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PRODUCT STAGE STATEMENTS Product stage statements are used on Texas Instruments data sheets to indicate the development stage(s) of the product(s) specified in the data sheets. If all products specified in a data sheet are at the same development stage, the appropriate statement from the following list is placed in the lower left corner of the first page of the data sheet. PRODUCTION DATA information is current as of publication date.
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General Information GTL GTLP ETL BTL/FB+ VME Application Reports Mechanical Data 1–1
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Contents Page Alphanumeric Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 General Information Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5 Explanation of Function Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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ALPHANUMERIC INDEX DEVICE SN54GTL16612 PAGE DEVICE SN74ABTE16245 . . . . . . . . . . . . . . . . 4–3 SN74ABTE16246 . . . . . . . . . . . . . . . 4–11 SN74FB1650 . . . . . . . . . . . . . . . . . . . . 5–3 SN74FB1651 . . . . . . . . . . . . . . . . . . . 5–11 SN74FB1653 . . . . . . . . . . . . . . . . . . . 5–21 SN74FB2031 . . . . . . . . . . . . . . . . . . . 5–31 SN74FB2033A . . . . . . . . . . . . . . . . . . 5–39 SN74FB2033K . . . . . . . . . . . . . . . . . . 5–51 SN74FB2040 . . . . . . . . . . . .
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GLOSSARY SYMBOLS, TERMS, AND DEFINITIONS INTRODUCTION These symbols, terms, and definitions are in accordance with those currently agreed upon by the JEDEC Council of the Electronic Industries Association (EIA) for use in the USA and by the International Electrotechnical Commission (IEC) for international use.
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GLOSSARY SYMBOLS, TERMS, AND DEFINITIONS IIH High-level input current The current into* an input when a high-level voltage is applied to that input IIL Low-level input current The current into* an input when a low-level voltage is applied to that input Ioff Input/output power-off leakage current The maximum leakage current into* an input or output terminal of the device with the specified voltage applied to the terminal and VCC = 0 V IOH High-level output current The current into* an output with inpu
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GLOSSARY SYMBOLS, TERMS, AND DEFINITIONS SR Slew rate The average rate of change (i.e.
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GLOSSARY SYMBOLS, TERMS, AND DEFINITIONS tPLH Propagation delay time, low-to-high level output The time between the specified reference points on the input and output voltage waveforms with the output changing from the defined low level to the defined high level tPLZ Disable time (of a 3-state output) from low level The time interval between the specified reference points on the input and the output voltage waveforms with the 3-state output changing from the defined low level to the high-impedance (off)
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GLOSSARY SYMBOLS, TERMS, AND DEFINITIONS tsu Setup time The time interval between the application of a signal at a specified input terminal and a subsequent active transition at another specified input terminal NOTES: 1. The setup time is the actual time interval between two signal events and is determined by the system in which the digital circuit operates. A minimum value is specified that is the shortest interval for which correct operation of the digital circuit is specified. 2.
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EXPLANATION OF FUNCTION TABLES The following symbols are used in function tables on TI data sheets: H L ↑ ↓ X Z a...
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EXPLANATION OF FUNCTION TABLES Among the most complex function tables are those of the shift registers. These embody most of the symbols used in any of the function tables, plus more. Below is the function table of a 4-bit bidirectional universal shift register.
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D-TYPE FLIP-FLOP AND LATCH SIGNAL CONVENTIONS It is normal TI practice to name the outputs and other inputs of a D-type flip-flop or latch and to draw its logic symbol based on the assumption of true data (D) inputs. Outputs that produce data in phase with the data inputs are called Q and those producing complementary data are called Q. An input that causes a Q output to go high or a Q output to go low is called preset (PRE).
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DEVICE NAMES AND PACKAGE DESIGNATORS * !$ 54 – Military 74 – Commercial Blank = No Options 2 – Series Damping Resistor on Outputs 4 – Level Shifter 25 – 25-Ω Line Driver (" ' #" Examples: Blank – Transistor-Transistor Logic ABT – Advanced BiCMOS Technology ABTE/ETL – Advanced BiCMOS Technology/ Enhanced Transceiver Logic AC/ACT – Advanced CMOS Logic AHC/AHCT – Advanced High-Speed CMOS Logic ALB – Advanced Low-Voltage BiCMOS ALS – Advanced Low-Power Schottky Logic ALVC – Advanced Low
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THERMAL INFORMATION In digital-system design, consideration must be given to thermal management of components. The small size of the small-outline packages makes this even more critical. Figures 1–5 show the high-effect (High-K) thermal resistance for the small-outline 14-, 16-, 20-, 24-, and 48-pin packages for various rates of airflow calculated in accordance with JESD 51-7. The thermal resistances in Figures 1–5 can be used to approximate typical and maximum virtual junction temperatures.
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THERMAL INFORMATION 120 110 DGV PW 100 90 80 70 DB D 60 50 40 30 20 10 0 R JA – Junction-to-Ambient Thermal Resistance – °C/W 16-Pin Packages 130 JUNCTION-TO-AMBIENT THERMAL RESISTANCE vs AIR VELOCITY θ θ R JA – Junction-to-Ambient Thermal Resistance – °C/W JUNCTION-TO-AMBIENT THERMAL RESISTANCE vs AIR VELOCITY 0 100 200 300 400 500 20-Pin Packages 130 120 110 100 90 80 70 DGV PW 60 DB 50 DW 40 30 20 10 0 0 100 Air Velocity – ft/min 110 100 90 80 PW DGV 70 60 DB 50 40 DW 30 2
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General Information GTL GTLP ETL BTL/FB+ VME Application Reports Mechanical Data 2–1
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Contents SN74GTL1655 Page 16-Bit LVTTL-to-GTL/GTL+ Universal Bus Transceiver With Live Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 GTL SN54GTL16612 SN74GTL16612 18-Bit LVTTL-to-GTL/GTL+ Universal Bus Transceivers . . . . 2–15 SN74GTL16616 17-Bit LVTTL-to-GTL/GTL+ Universal Bus Transceiver With Buffered Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23 SN74GTL16622A 18-Bit LVTTL-to-GTL/GTL+ Bus Transceiver . . . . . . . . . . . . .
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SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH LIVE INSERTION SCBS696G – JULY 1997 – REVISED AUGUST 2001 D Member of Texas Instruments’ Widebus D D D D D D D D Family UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Translates Between GTL/GTL+ Signal Level and LVTTL Logic Levels High-Drive (100 mA), Low-Output-Impedance (12 Ω) Bus Tr
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SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH LIVE INSERTION SCBS696G – JULY 1997 – REVISED AUGUST 2001 description (continued) The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
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SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH LIVE INSERTION SCBS696G – JULY 1997 – REVISED AUGUST 2001 Function Tables FUNCTION† INPUTS LEAB CLK A OUTPUT B H X X X Z Isolation L H X L L Transparent L H X H H Transparent L L ↑ L L Registered L L ↑ H Registered L L H H B0‡ OEAB X MODE Previous state B0§ Previous state † A-to-B data flow is shown. B-to-A flow is similar, but uses OEBA, LEBA, and CLK.
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SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH LIVE INSERTION SCBS696G – JULY 1997 – REVISED AUGUST 2001 logic diagram (positive logic) 41 VREF 61 VERC 64 CLK 63 1LEAB 62 1LEBA 1OEBA 2 1 1OEAB 33 OE 1A1 4 1D C1 CLK 1D C1 CLK To Seven Other Channels 2–6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 59 1B1
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SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH LIVE INSERTION SCBS696G – JULY 1997 – REVISED AUGUST 2001 logic diagram (positive logic) (continued) 41 VREF 61 VERC 64 CLK 35 2LEAB 34 2LEBA 2OEBA 32 31 2OEAB 33 OE 2A1 17 1D C1 48 2B1 CLK 1D C1 CLK To Seven Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–7
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SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH LIVE INSERTION SCBS696G – JULY 1997 – REVISED AUGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC, BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): A-port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
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SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH LIVE INSERTION SCBS696G – JULY 1997 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range, VREF = 1 V and VTT = 1.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH A port VCC = 3 V, VCC = 3 V to 3.6 V, II = –18 mA IOH = –100 µA VCC = 3 V IOH = –12 mA IOH = –24 mA VCC = 3 V to 3.6 V, A port VCC = 3 V VOL B port VCC = 3 V Control inputs II VCC = 3 3.
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SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH LIVE INSERTION SCBS696G – JULY 1997 – REVISED AUGUST 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2 V, VREF = 0.8 V, and VERC = VCC or GND for GTL (unless otherwise noted) MIN fclock Clock frequency tw Pulse duration LE high 3 CLK high or low 3 Data before CLK↑ tsu th Setup time Data before LE↓ Data after LE↓ UNIT 160 MHz ns 2.7 CLK high 2.8 CLK low 2.
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SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH LIVE INSERTION SCBS696G – JULY 1997 – REVISED AUGUST 2001 B-to-A switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2 V and VREF = 0.8 V for GTL (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL ten tdis FROM (INPUT) TO (OUTPUT) MIN MAX 160 B A CLK A LEBA A OEBA or OE A UNIT MHz 1.8 4.7 2.3 4.6 1.6 4 1.5 3.4 1.7 4 1.4 3.5 1.3 4.2 2 6.
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SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH LIVE INSERTION SCBS696G – JULY 1997 – REVISED AUGUST 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V, VREF = 1 V, and VERC = VCC or GND for GTL+ (unless otherwise noted) MIN fclock Clock frequency tw Pulse duration tsu Setup time LE high 3 CLK high or low 3 Data before CLK↑ th Data before LE↓ Data after LE↓ UNIT 160 MHz ns 2.7 CLK high 2.8 CLK low 2.
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SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH LIVE INSERTION SCBS696G – JULY 1997 – REVISED AUGUST 2001 B-to-A switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL ten tdis ten tdis FROM (INPUT) TO (OUTPUT) MIN MAX 160 B A CLK A LEBA A OEBA A OE A UNIT MHz 2 4.8 2.4 4.7 1.6 4.4 1.5 3.4 1.7 4 1.4 3.5 1.3 4.
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SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH LIVE INSERTION SCBS696G – JULY 1997 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION VTT 6V 500 Ω From Output Under Test S1 Open CL = 50 pF (see Note A) 500 Ω 12.5 Ω From Output Under Test CL = 30 pF (see Note A) S1 Open 6V GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V Input 3V Timing Input 1.5 V 0V 1.5 V 1.
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SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS SCBS480K – JUNE 1994 – REVISED AUGUST 2001 D Members of Texas Instruments’ Widebus D D D D D D D D D Family UBT Transceivers Combine D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Translate Between GTL/GTL+ Signal Levels and LVTTL Logic Levels Support Mixed-Mode (3.
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SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS SCBS480K – JUNE 1994 – REVISED AUGUST 2001 description (continued) Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable(LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high.
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SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS SCBS480K – JUNE 1994 – REVISED AUGUST 2001 logic diagram (positive logic) 35 VREF 1 OEAB CEAB 56 55 CLKAB 2 LEAB 28 LEBA 30 CLKBA CEBA 29 27 OEBA CE 1D 3 A1 54 B1 C1 CLK CE 1D C1 CLK To 17 Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–17
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SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS SCBS480K – JUNE 1994 – REVISED AUGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC: 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
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SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS SCBS480K – JUNE 1994 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL A portt A port B port Control inputs II A port B port Ioff II(hold) ( ) IOZH IOZL ICC (3.3 (3 3 V) ICC (5 V) Ciio VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V II = –18 mA VCC (3.3 V)= 3.15 V to 3.45 V, VCC (5 V) = 4.75 V to 5.
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SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS SCBS480K – JUNE 1994 – REVISED AUGUST 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2 V and VREF = 0.8 V for GTL (unless otherwise noted) (see Figure 1) SN54GTL16612 MIN fclock tw tsu th SN74GTL16612 MAX Clock frequency MIN 95 Pulse duration Setup time Hold time MAX 95 LEAB or LEBA high 3.3 3.3 CLKAB or CLKBA high or low 5.6 5.
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SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS SCBS480K – JUNE 1994 – REVISED AUGUST 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (unless otherwise noted) (see Figure 1) SN54GTL16612 MIN fclock tw tsu th SN74GTL16612 MAX Clock frequency MIN 95 Pulse duration Setup time Hold time MAX 95 LEAB or LEBA high 3.3 3.3 CLKAB or CLKBA high or low 5.6 5.6 A before CLKAB↑ 1.
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SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS SCBS480K – JUNE 1994 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION VTT = 1.2 V, VREF = 0.8 V FOR GTL AND VTT = 1.5 V, VREF = 1 V FOR GTL+ VTT 6V 500 Ω From Output Under Test CL = 50 pF (see Note A) S1 Open 25 Ω TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND 500 Ω S1 Open 6V GND From Output Under Test CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V VM V Input 3V Timing Input 1.
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SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCBS481H – JUNE 1994 – REVISED AUGUST 2001 D Member of Texas Instruments’ Widebus D D D D D D D D D D D Family UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference GTL Buffered CLKAB Signal (CLKOUT) Translates Between GTL/GTL+ Signal Levels and LVTTL Lo
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SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCBS481H – JUNE 1994 – REVISED AUGUST 2001 description (continued) Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high.
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SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCBS481H – JUNE 1994 – REVISED AUGUST 2001 logic diagram (positive logic) VREF OEAB CEAB CLKAB LEAB LEBA CLKBA CEBA OEBA A1 35 1 56 55 2 28 30 29 27 CE 1D 3 CE 1D C1 CLK 54 C1 CLK B1 1 of 17 Channels 31 CLKIN CLKOUT 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–25
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SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCBS481H – JUNE 1994 – REVISED AUGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC: 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
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SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCBS481H – JUNE 1994 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL A port VCC (3 (3.3 3 V) = 3.15 3 15 V, V VCC (5 V) = 4 4.75 75 V IOH = –8 mA IOH = –32 mA TYP† –1.2 VCC–0.2 2.4 V IOL = 100 µA IOL = 16 mA 0.2 IOL = 32 mA IOL = 64 mA 0.5 0.4 VCC (5 V) = 4 4.75 75 V B port VCC (3.3 V) = 3.
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SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCBS481H – JUNE 1994 – REVISED AUGUST 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2 V and VREF = 0.8 V for GTL (unless otherwise noted) (see Figure 1) MIN fclock tw tsu th 2–28 Clock frequency Pulse duration Setup time Hold time POST OFFICE BOX 655303 LEAB or LEBA high 3.3 CLKAB or CLKBA high or low 5.5 A before CLKAB↑ 1.
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SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCBS481H – JUNE 1994 – REVISED AUGUST 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2 V and VREF = 0.8 V for GTL (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tr tf tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL ten tdis FROM (INPUT) TO (OUTPUT) TYP† MAX 1.7 3 4.4 1.4 2.8 4.5 2.3 3.8 5.4 2.2 3.7 5.3 2.
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SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCBS481H – JUNE 1994 – REVISED AUGUST 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (unless otherwise noted) (see Figure 1) MIN fclock Clock frequency tw Pulse duration tsu th 2–30 Setup time Hold time POST OFFICE BOX 655303 LEAB or LEBA high 3.3 CLKAB or CLKBA high or low 5.5 A before CLKAB↑ 1.
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SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCBS481H – JUNE 1994 – REVISED AUGUST 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tr tf tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL ten tdis FROM (INPUT) TO (OUTPUT) TYP† MAX 1.7 3 4.4 1.4 2.9 4.6 2.3 3.8 5.4 2.2 3.7 5.4 2.
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SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCBS481H – JUNE 1994 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION VTT = 1.2 V, VREF = 0.8 V FOR GTL AND VTT = 1.
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SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS673F – AUGUST 1996 – REVISED AUGUST 2001 D Member of Texas Instruments’ Widebus D D D D D D D D D DGG PACKAGE (TOP VIEW) Family OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference D-Type Flip-Flops With Qualified Storage Enable Translates Between GTL/GTL+ Signal Levels and LVTTL Logic Levels Supports Mixed-Mode (3.
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SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS673F – AUGUST 1996 – REVISED AUGUST 2001 description (continued) Data flow in each direction is controlled by the output-enable (OEAB and OEBA) and clock (CLKAB and CLKBA) inputs. The clock-enable (CEAB and CEBA) inputs control each 9-bit transceiver independently, which makes the device more versatile. For A-to-B data flow, the device operates on the low-to-high transition of CLKAB if CEAB is low. When OEAB is low, the outputs are active.
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SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS673F – AUGUST 1996 – REVISED AUGUST 2001 logic diagram (positive logic) VREF OEAB 1CEAB CLKAB CLKBA 1CEBA OEBA 1A1 40 1 63 64 33 62 32 CE 2 61 1D 1B1 CLK CE 1D CLK To Eight Other Channels 2CEAB 2CEBA 2A1 34 35 CE 17 1D 48 2B1 CLK CE 1D CLK To Eight Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–35
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SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS673F – AUGUST 1996 – REVISED AUGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): A-port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V B port and VREF . . . . . . .
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SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS673F – AUGUST 1996 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range for GTL/GTL+ (unless otherwise noted) PARAMETER VIK VOH A port TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.15 3 15 V IOH = –12 mA IOH = –24 mA V VCC–0.2 2.4 V 2 0.5 VCC = 3.15 V to 3.45 V, 0.2 VCC = 3.15 V IOL = 10 mA IOL = 40 mA B port VCC = 3.
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SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS673F – AUGUST 1996 – REVISED AUGUST 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature for GTL (unless otherwise noted) MIN fclock tw Clock frequency Pulse duration, CLK high or low tsu Setup time th Hold time MAX UNIT 200 MHz 2.5 Data before CLK↑ 2.1 CE before CLK↑ 3.3 Data after CLK↑ 0.
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SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS673F – AUGUST 1996 – REVISED AUGUST 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature for GTL+ (unless otherwise noted) MIN fclock tw Clock frequency Pulse duration, CLK high or low tsu Setup time th Hold time MAX UNIT 200 MHz 2.5 Data before CLK↑ 2.4 CE before CLK↑ 3.2 Data after CLK↑ 0.
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SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS673F – AUGUST 1996 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION VTT 6V S1 500 Ω From Output Under Test Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND CL = 50 pF (see Note A) 500 Ω 25 Ω S1 Open 6V GND From Output Under Test CL = 30 pF (see Note A) LOAD CIRCUIT FOR A OUTPUTS Test Point LOAD CIRCUIT FOR B OUTPUTS tw 3V 3V Input 1.5 V 1.5 V Timing Input 1.
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SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS674G – AUGUST 1996 – REVISED AUGUST 2001 D Member of Texas Instruments’ Widebus D D D D D D D D D Family OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference D-Type Flip-Flops With Qualified Storage Enable Translates Between GTL/GTL+ Signal Levels and LVTTL Logic Levels Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltages With 3.
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SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS674G – AUGUST 1996 – REVISED AUGUST 2001 description (continued) Data flow in each direction is controlled by the output-enable (OEAB and OEBA) and clock (CLKAB and CLKBA) inputs. The clock-enable (CEAB and CEBA) inputs enable or disable the clock for all 18 bits at a time. However, OEAB and OEBA are designed to control each 9-bit transceiver independently, which makes the device more versatile.
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SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS674G – AUGUST 1996 – REVISED AUGUST 2001 logic diagram (positive logic) 40 VREF 63 1OEAB 1 CEAB 64 CLKAB 33 CLKBA 32 CEBA 1OEBA 62 CE 2 1A1 61 1B1 1D CLK CE 1D CLK To Eight Other Channels 34 2OEAB 2OEBA 2A1 35 CE 17 1D 48 2B1 CLK CE 1D CLK To Eight Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–43
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SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS674G – AUGUST 1996 – REVISED AUGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
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SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS674G – AUGUST 1996 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range for GTL/GTL+ (unless otherwise noted) PARAMETER VIK VOH A port TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3 3.15 15 V IOH = –12 mA IOH = –24 mA V VCC–0.2 2.4 V 2 0.5 VCC = 3.15 V to 3.45 V, 0.2 VCC = 3.15 V IOL = 10 mA IOL = 40 mA B port VCC = 3.45 V, IOL = 50 mA VI = 5.
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SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS674G – AUGUST 1996 – REVISED AUGUST 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature for GTL (unless otherwise noted) MIN fclock tw Clock frequency Pulse duration, CLK high or low tsu Setup time th Hold time MAX UNIT 200 MHz 2.5 Data before CLK↑ 2.6 CE before CLK↑ 3.3 Data after CLK↑ 0.
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SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS674G – AUGUST 1996 – REVISED AUGUST 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature for GTL+ (unless otherwise noted) MIN fclock tw Clock frequency Pulse duration, CLK high or low tsu Setup time th Hold time MAX UNIT 200 MHz 2.5 Data before CLK↑ 2.3 CE before CLK↑ 3.3 Data after CLK↑ 0.
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SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS674G – AUGUST 1996 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION VTT = 1.5 V, VREF = 1 V VTT 6V 500 Ω From Output Under Test S1 Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND CL = 50 pF (see Note A) 500 Ω 25 Ω From Output Under Test S1 Open 6V GND Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS 3V Timing Input tw 1.5 V 0V 3V 1.5 V Input 1.
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General Information GTL GTLP ETL BTL/FB+ VME Application Reports Mechanical Data 3–1
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Contents SN74GTLPH306 Page 8-Bit LVTTL-to-GTLP Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3 GTLP SN74GTLP817 GTLP-to-LVTTL 1-to-6 Fanout Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11 SN74GTLP1394 2-Bit LVTTL-to-GTLP Adjustable-Edge-Rate Bus Transceiver With Split LVTTL Port, Feedback Path, and Selectable Polarity . . . . . . . . . . . .
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SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES284E – OCTOBER 1999 – REVISED AUGUST 2001 D TI-OPC Circuitry Limits Ringing on D D D D D D D D D D DGV, DW, OR PW PACKAGE (TOP VIEW) Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels LVTTL Interfaces Are 5-V Tolerant Medium-Drive GTLP Outputs (50 mA) LVTTL Outputs (–24 mA/24 mA) GTLP Rise and Fall Times Designed for Opti
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SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES284E – OCTOBER 1999 – REVISED AUGUST 2001 description (continued) This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
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SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES284E – OCTOBER 1999 – REVISED AUGUST 2001 logic diagram (positive logic) 24 DIR 1 OE A1 22 3 B1 23 VREF To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): A port and control inputs . . . . .
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SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES284E – OCTOBER 1999 – REVISED AUGUST 2001 recommended operating conditions (see Notes 4 through 7) VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK IOH Input clamp current Low-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate NOM MAX UNIT V 3.15 3.3 3.45 GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.
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SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES284E – OCTOBER 1999 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.15 V IOH = –12 mA IOH = –24 mA VCC = 3.15 V to 3.45 V, A port VOL B port A-port and control inputs II‡ VCC = 3.15 V VCC = 3.15 V VCC = 3.
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SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES284E – OCTOBER 1999 – REVISED AUGUST 2001 hot-insertion specifications for B port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, VI or VO = 0 to 1.5 V VO = 0.5 V to 1.5 V, 10 µA OE = 0 ±30 µA IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 1.
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SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES284E – OCTOBER 1999 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω 25 Ω From Output Under Test CL = 30 pF (see Note A) S1 Open 6V GND LOAD CIRCUIT FOR A OUTPUTS Test Point LOAD CIRCUIT FOR B OUTPUTS 3V 1.5 V Input 1.
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SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES284E – OCTOBER 1999 – REVISED AUGUST 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation is shown in Figure 2.
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SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER SCES285E – OCTOBER 1999 – REVISED AUGUST 2001 D OEC Circuitry Improves Signal Integrity D D D D D D D D D D D DGV, DW, OR PW PACKAGE (TOP VIEW) and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels GTLP-to-LVTTL 1-to-6 Fanout Driver LVTTL-to-GTLP 1-to-2 Fanout Driver LVTTL Interfaces Are 5-V Tolerant Medium-Drive GTLP Outputs (50 mA) Reduced-Drive LVTTL Outputs (–12 mA/12 mA) Variable Edge-Rate C
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SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER SCES285E – OCTOBER 1999 – REVISED AUGUST 2001 description (continued) This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
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SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER SCES285E – OCTOBER 1999 – REVISED AUGUST 2001 Function Tables OUTPUT CONTROL (A to B) INPUTS AI OEAB OUTPUT BOn MODE Isolation X H Z H L L L L H Inverted transparent OUTPUT CONTROL (B to A) INPUTS BI OEBA OUTPUT AOn MODE Isolation X H Z H L L L L H Inverted transparent B-PORT EDGE-RATE CONTROL (ERC) INPUT ERC LOGIC LEVEL NOMINAL VOLTAGE H VCC GND L OUTPUT B-PORT EDGE RATE Slow Fast logic diagram (positive logic) 23 18 22 OEAB
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SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER SCES285E – OCTOBER 1999 – REVISED AUGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Ground dc voltage difference, (|VGNDG – VGNDT|) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.
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SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER SCES285E – OCTOBER 1999 – REVISED AUGUST 2001 recommended operating conditions (see Notes 4 through 7) VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage MIN NOM MAX UNIT V 3.15 3.3 3.45 GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 VCC VTT 5.5 V VCC 5.5 V BI AI, OE BI ERC AI, OE VREF+0.05 VCC–0.
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SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER SCES285E – OCTOBER 1999 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH AO port AO port TEST CONDITIONS II BI, AI, OE, ERC AO port IOZH BO port AO port IOZL ICC ∆ICC‡ Ci Co BO port AO or BO port AI, OE AI, OE, ERC BI AO port BO port TYP† MAX UNIT –1.2 V VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.
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SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER SCES285E – OCTOBER 1999 – REVISED AUGUST 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.
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SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER SCES285E – OCTOBER 1999 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 Ω From Output Under Test S1 Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND CL = 50 pF (see Note A) 500 Ω 25 Ω S1 Open 6V GND From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR BO PORTS LOAD CIRCUIT FOR AO PORTS 3V 1.5 V Input 1.
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SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER SCES285E – OCTOBER 1999 – REVISED AUGUST 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation is shown in Figure 2.
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SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286E – OCTOBER 1999 – REVISED AUGUST 2001 D TI-OPC Circuitry Limits Ringing on D D D D D D D D D D D D, DGV, OR PW PACKAGE (TOP VIEW) Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels Split LVTTL Port Provides a Feedback Path for Control
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SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286E – OCTOBER 1999 – REVISED AUGUST 2001 description (continued) This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286E – OCTOBER 1999 – REVISED AUGUST 2001 Function Tables OUTPUT CONTROL INPUTS OUTPUT MODE H Z Isolation L H A data to B bus H L B data to Y bus L L A data to B bus, B data to Y bus L L H Inverted A data to B bus L H L Inverted B data to Y bus L L L Inverted A data to B bus, Inverted B data to Y bus T/C OEAB OEBY X H H H H True transparent
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SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286E – OCTOBER 1999 – REVISED AUGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): A inputs, ERC, and control inputs . . . . . . . . . . . . . .
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SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286E – OCTOBER 1999 – REVISED AUGUST 2001 recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage MIN NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 VCC VTT 5.
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SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286E – OCTOBER 1999 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH Y outputs TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.15 V IOH = –12 mA IOH = –24 mA VCC = 3.15 V to 3.45 V, Y outputs VCC = 3.
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SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286E – OCTOBER 1999 – REVISED AUGUST 2001 live-insertion specifications for B port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, BIAS VCC = 0, VI or VO = 0 to 1.5 V VO = 0.5 V to 1.5 V, OE = 0 10 µA BIAS VCC = 0, ±30 µA IOZPD VCC = 1.5 V to 0, VCC = 0 to 3.
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SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286E – OCTOBER 1999 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 Ω From Output Under Test S1 Open 12.5 Ω From Output Under Test CL = 30 pF (see Note A) GND CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω S1 Open 6V GND LOAD CIRCUIT FOR Y OUTPUTS Test Point LOAD CIRCUIT FOR B OUTPUTS 3V 1.5 V Input 1.
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SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286E – OCTOBER 1999 – REVISED AUGUST 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation is shown in Figure 2.
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SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286E – OCTOBER 1999 – REVISED AUGUST 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.
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SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286E – OCTOBER 1999 – REVISED AUGUST 2001 APPLICATION INFORMATION operational description The GTLP1394 is specifically designed for use with the Texas Instruments 1394 backplane layer controller family to transmit the 1394 backplane serial bus across parallel backplanes.
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SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286E – OCTOBER 1999 – REVISED AUGUST 2001 APPLICATION INFORMATION protocol Both asynchronous and isochronous data transfers are supported. The asynchronous format transfers data and transaction-layer information to an explicit address. The isochronous format broadcasts data based on channel numbers rather than specific addressing.
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SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286E – OCTOBER 1999 – REVISED AUGUST 2001 APPLICATION INFORMATION SN74GTLP1394 interface with the TSB14AA1 1394 backplane PHY D D D D A1, B1, and Y1 are used for the PHY data signals. D D D D D T/C is connected to GND for inverted signals. A2, B2, and Y2 are used for the PHY strobe signals.
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SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286E – OCTOBER 1999 – REVISED AUGUST 2001 APPLICATION INFORMATION logical representation VCC TSB14AA1 3.
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SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286E – OCTOBER 1999 – REVISED AUGUST 2001 APPLICATION INFORMATION physical representation 64-Bit Data Bus 32- to 64-Bit Address Bus GTLP1394 Transceiver 1394 Backplane PHY 1394 Link-Layer Controller Host Microprocessor Terminators Backplane Trace Connectors VME/FB+/CPCI or GTLP Transceivers STRB A2 Module Module Module Node Node Node PHY PHY PHY Y2 A1 Y1 V
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SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349B – JUNE 2001 – REVISED AUGUST 2001 D TI-OPC Circuitry Limits Ringing on D D D D D D D D 1Y 1T/C 2Y GND 1OEAB VCC 1A GND 2A 2OEAB 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 1OEBY 2T/C 2OEBY GND 1B ERC 2B GND VREF BIAS VCC description The SN74GTLP1395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and G
PAGE 105
SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349B – JUNE 2001 – REVISED AUGUST 2001 description (continued) This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349B – JUNE 2001 – REVISED AUGUST 2001 functional description The output-enable (1OEAB, 1OEBY) and polarity-control (1T/C) inputs control 1A, 1B, and 1Y. 2OEAB, 2OEBY, and 2T/C control 2A, 2B, and 2Y. OEAB controls the activity of the B port. When OEAB is low, the B-port output is active. When OEAB is high, the B-port output is disabled.
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SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349B – JUNE 2001 – REVISED AUGUST 2001 logic diagram (positive logic) 12 VREF 15 ERC 5 1OEAB 1T/C 1A 2 7 16 1B 20 1OEBY 1Y 1 10 PRODUCT PREVIEW 2OEAB 2T/C 2A 19 14 9 18 2OEBY 3 2Y Pin numbers shown are for the DGV, DW, and PW packages.
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SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349B – JUNE 2001 – REVISED AUGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
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SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349B – JUNE 2001 – REVISED AUGUST 2001 PRODUCT PREVIEW recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK IOH Input clamp current Low-level output current ∆t/∆v Input transition rise or fall ra
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SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349B – JUNE 2001 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) VIK VOH TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, Y outputs II = –18 mA IOH = –100 µA IOH = –12 mA VCC = 3.15 V IOH = –24 mA VCC = 3.15 V to 3.45 V, Y outputs VCC = 3.
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SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349B – JUNE 2001 – REVISED AUGUST 2001 PRODUCT PREVIEW switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.
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SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349B – JUNE 2001 – REVISED AUGUST 2001 skew characteristics over recommended ranges of supply voltage and operating free-air temperature, VREF = 1 V, standard lumped loads (CL = 30 pF for B port and CL = 50 pF for Y port) (unless otherwise noted)(see Figure 1)† PARAMETER FROM (INPUT) TO (OUTPUT) EDGE RATE‡ tsk(LH)¶ tsk(HL)¶ A B Slow ns tsk(LH)¶ tsk(HL)¶ A B
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SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349B – JUNE 2001 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 Ω From Output Under Test S1 Open 12.5 Ω From Output Under Test CL = 30 pF (see Note A) GND CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω S1 Open 6V GND LOAD CIRCUIT FOR Y OUTPUTS Test Point LOAD CIRCUIT FOR B OUTPUTS 3V 1.5 V Input 1.
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SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349B – JUNE 2001 – REVISED AUGUST 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation is shown in Figure 2.
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SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349B – JUNE 2001 – REVISED AUGUST 2001 APPLICATION INFORMATION operational description The GTLP1395 is designed specifically for use with the TI 1394 backplane layer controller family to transmit the 1394 backplane serial bus across parallel backplanes.
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SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349B – JUNE 2001 – REVISED AUGUST 2001 APPLICATION INFORMATION protocol The backplane physical layer shares some commonality with the cable physical layer. Common functions include: bus-state determination, bus-access protocols, encoding and decoding functions, and synchronization of received data to a local clock.
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SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349B – JUNE 2001 – REVISED AUGUST 2001 APPLICATION INFORMATION SN74GTLP1395 interface with the TSB14AA1 1394 backplane PHY D D D D PRODUCT PREVIEW D D D D D 1A, 1B, and 1Y are used for the PHY data signals. 2A, 2B, and 2Y are used for the PHY strobe signals. PHY N_OEB_D or OCDOE connects to 1OEAB and 2OEAB, which control the PHY transmit signals.
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SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349B – JUNE 2001 – REVISED AUGUST 2001 APPLICATION INFORMATION physical representation 64-Bit Data Bus 32- to 64-Bit Address Bus GTLP1395 Transceiver 1394 Backplane PHY 1394 Link-Layer Controller Host Microprocessor PRODUCT PREVIEW Terminators Backplane Trace Connectors VME/FB+/CPCI or GTLP Transceivers STRB 2A Module Module Module Node Node Node PHY PHY
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SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350B – JUNE 2001 – REVISED AUGUST 2001 D TI-OPC Circuitry Limits Ringing on D D D D D D D D D 1Y 1T/C 2Y GND 1OEAB VCC 1A GND 2A 2OEAB 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 1OEBY 2T/C 2OEBY GND 1B ERC 2B GND VREF BIAS VCC description The SN74GTLP21395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP a
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SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350B – JUNE 2001 – REVISED AUGUST 2001 description (continued) Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL or 5-V CMOS devices. VREF is the B-port differential input reference voltage.
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SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350B – JUNE 2001 – REVISED AUGUST 2001 functional description The output-enable (1OEAB, 1OEBY) and polarity-control (1T/C) inputs control 1A, 1B, and 1Y. 2OEAB, 2OEBY, and 2T/C control 2A, 2B, and 2Y. OEAB controls the activity of the B port. When OEAB is low, the B-port output is active. When OEAB is high, the B-port output is disabled.
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SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350B – JUNE 2001 – REVISED AUGUST 2001 logic diagram (positive logic) 12 VREF 15 ERC 5 1OEAB 1T/C 1A 2 7 16 1B 20 1OEBY 1Y 1 10 PRODUCT PREVIEW 2OEAB 2T/C 2A 19 14 9 18 2OEBY 3 2Y Pin numbers shown are for DGV, DW, and PW packages.
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SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350B – JUNE 2001 – REVISED AUGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
PAGE 124
SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350B – JUNE 2001 – REVISED AUGUST 2001 PRODUCT PREVIEW recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK IOH Input clamp current Low-level output current ∆t/∆v Input transition rise or fall r
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SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350B – JUNE 2001 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) VIK VOH TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, Y outputs II = –18 mA IOH = –100 µA IOH = –6 mA VCC = 3.15 V IOH = –12 mA VCC = 3.15 V II‡ IOZ‡ ICC VCC = 3.15 V UNIT –1.2 V V 2 0.2 0.55 0.
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SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350B – JUNE 2001 – REVISED AUGUST 2001 PRODUCT PREVIEW switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.
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SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350B – JUNE 2001 – REVISED AUGUST 2001 skew characteristics over recommended ranges of supply voltage and operating free-air temperature, VREF = 1 V, standard lumped loads (CL = 30 pF for B port and CL = 50 pF for Y port) (unless otherwise noted)(see Figure 1)† PARAMETER FROM (INPUT) TO (OUTPUT) EDGE RATE‡ tsk(LH)¶ tsk(HL)¶ A B Slow ns tsk(LH)¶ tsk(HL)¶ A
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SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350B – JUNE 2001 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 Ω From Output Under Test S1 Open 12.5 Ω From Output Under Test CL = 30 pF (see Note A) GND CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω S1 Open 6V GND LOAD CIRCUIT FOR Y OUTPUTS Test Point LOAD CIRCUIT FOR B OUTPUTS 3V 1.5 V Input 1.
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SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350B – JUNE 2001 – REVISED AUGUST 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation is shown in Figure 2.
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SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350B – JUNE 2001 – REVISED AUGUST 2001 APPLICATION INFORMATION operational description The GTLP21395 is designed specifically for use with the TI 1394 backplane layer controller family to transmit the 1394 backplane serial bus across parallel backplanes.
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SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350B – JUNE 2001 – REVISED AUGUST 2001 APPLICATION INFORMATION protocol The backplane physical layer shares some commonality with the cable physical layer. Common functions include: bus-state determination, bus-access protocols, encoding and decoding functions, and synchronization of received data to a local clock.
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SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350B – JUNE 2001 – REVISED AUGUST 2001 APPLICATION INFORMATION SN74GTLP21395 interface with the TSB14AA1 1394 backplane PHY D D D D PRODUCT PREVIEW D D D D D 1A, 1B, and 1Y are used for the PHY data signals. 2A, 2B, and 2Y are used for the PHY strobe signals. PHY N_OEB_D or OCDOE connects to 1OEAB and 2OEAB, which control the PHY transmit signals.
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SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350B – JUNE 2001 – REVISED AUGUST 2001 APPLICATION INFORMATION physical representation 64-Bit Data Bus 32- to 64-Bit Address Bus GTLP21395 Transceiver 1394 Backplane PHY 1394 Link-Layer Controller Host Microprocessor PRODUCT PREVIEW Terminators Backplane Trace Connectors VME/FB+/CPCI or GTLP Transceivers STRB 2A Module Module Module Node Node Node PHY PH
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SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D – OCTOBER 1999 – REVISED AUGUST 2001 D Member of the Texas Instruments’ D D D D D D D D D D D D D DGG PACKAGE (TOP VIEW) Widebus Family UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference B
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SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D – OCTOBER 1999 – REVISED AUGUST 2001 description (continued) Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage. This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC.
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SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D – OCTOBER 1999 – REVISED AUGUST 2001 functional description The SN74GTLPH1612 is a high-drive (100 mA), 18-bit UBT transceiver containing D-type latches and D-type flip-flops for data-path operation in transparent, latched, clocked, or clock-enabled modes and can replace any of the functions shown in Table 1. Data polarity is noninverting. Table 1.
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SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D – OCTOBER 1999 – REVISED AUGUST 2001 Function Tables OUTPUT ENABLE† INPUTS CEAB OEAB LEAB X H L L L OUTPUT B MODE X Z Isolation X B0‡ B0§ Latched storage of A data CLKAB A X X L H L L L X X L H X L L X L H X H H L L L ↑ L L L L L ↑ H H B0§ True transparent Clocked storage of A data H L L X X Clock inhibit † A-to-B data flow is shown: B-to-A data flow is similar, but
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SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D – OCTOBER 1999 – REVISED AUGUST 2001 logic diagram (positive logic) 39 VREF 28 ERC 1 OEAB CEAB 64 63 CLKAB 2 LEAB 32 LEBA 34 CLKBA CEBA 33 31 OEBA CE 1D 3 A1 62 B1 C1 CLK CE 1D C1 CLK To 17 Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3–73
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SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D – OCTOBER 1999 – REVISED AUGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): A port, ERC, and control inputs . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V B port and VREF . . . .
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SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D – OCTOBER 1999 – REVISED AUGUST 2001 recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage MIN NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 VCC VTT 5.5 V VCC 5.
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SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D – OCTOBER 1999 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.15 V IOH = –12 mA IOH = –24 mA VCC = 3.15 V to 3.45 V, A port VCC = 3.15 V VOL II TYP† MAX UNIT –1.2 V VCC–0.2 2.
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SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D – OCTOBER 1999 – REVISED AUGUST 2001 live-insertion specifications for B port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, BIAS VCC = 0, VI or VO = 0 to 1.5 V VO = 0.5 V to 1.5 V, OE = 0 10 µA BIAS VCC = 0, ±30 µA IOZPD VCC = 1.5 V to 0, VCC = 0 to 3.15 V BIAS VCC = 0, VO = 0.5 V to 1.
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SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D – OCTOBER 1999 – REVISED AUGUST 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (normal mode) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL ten tdis ten tdis FROM (INPUT) TO (OUTPUT) EDGE RATE† MAX 4.2 5.6 7.1 3 4.4 6.
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SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D – OCTOBER 1999 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 Ω From Output Under Test S1 Open CL = 50 pF (see Note A) 500 Ω 12.5 Ω S1 Open 6V GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V 3V 1.5 V Input 1.5 V Timing Input 1.
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SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D – OCTOBER 1999 – REVISED AUGUST 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation is shown in Figure 2.
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SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D – OCTOBER 1999 – REVISED AUGUST 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.
PAGE 147
SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 D Member of Texas Instruments’ Widebus D D D D D D D D D D D D D D DGG PACKAGE (TOP VIEW) Family UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Elec
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SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 description (continued) GTLP is the Texas Instruments (TI) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH1616 is given only at the preferred higher noise margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.
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SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 functional description The SN74GTLPH1616 is a high-drive (100 mA), 17-bit UBT transceiver containing D-type latches and D-type flip-flops for data-path operation in transparent, latched, clocked, or clock-enabled modes and can replace any of the functions shown in Table 1. Data polarity is noninverting. Table 1.
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SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 Function Tables OUTPUT ENABLE† INPUTS CEAB OEAB LEAB X H L L L OUTPUT B MODE X Z Isolation X B0‡ B0§ Latched storage of A data CLKAB A X X L H L L L X X L H X L L X L H X H H L L L ↑ L L L L L ↑ H H B0§ True transparent Clocked storage of A data H L L X X Clock inhibit † A-to-B data flow is shown: B-to-A
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SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 logic diagram (positive logic) VREF ERC OEAB CEAB CLKAB LEAB LEBA CLKBA CEBA OEBA A1 39 28 1 64 63 2 32 34 33 31 CE 1D 3 CE 1D C1 CLK 62 C1 CLK B1 1 of 17 Channels 35 CLKIN CLKOUT 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3–87
PAGE 152
SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): A-port, ERC, and control inputs . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 153
SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage MIN NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 VCC VTT 5.5 V VCC 5.
PAGE 154
SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.15 V IOH = –12 mA IOH = –24 mA VCC = 3.15 V to 3.45 V, A port VCC = 3.15 V VOL II TYP† MAX UNIT –1.2 V VCC–0.2 2.
PAGE 155
SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 live-insertion specifications for B port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, BIAS VCC = 0, VI or VO = 0 to 1.5 V VO = 0.5 V to 1.5 V, OE = 0 10 µA BIAS VCC = 0, ±30 µA IOZPD VCC = 1.5 V to 0, VCC = 0 to 3.15 V BIAS VCC = 0, VO = 0.5 V to 1.
PAGE 156
SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.
PAGE 157
SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 Ω From Output Under Test S1 Open CL = 50 pF (see Note A) 500 Ω 12.5 Ω S1 Open 6V GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V 3V 1.5 V Input 1.5 V Timing Input 1.
PAGE 158
SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (see Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation is shown in Figure 2.
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SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.
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SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001 D Member of the Texas Instruments D D D D D D D D D D description DIR OE A1 A2 GND A3 VCC A4 A5 CMS A6 GND A7 A8 A9 VCC A10 GND A11 A12 GND A13 A14 GND A15 VCC A16 GND A17 A18 CLKOUT CKOE 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 F
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SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001 description (continued) GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH1627 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.
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SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001 functional description The SN74GTLPH1627 is a high-drive (100 mA), 18-bit bus transceiver containing D-type latches and D-type flip-flops for data-path operation in transparent or latched modes and can replace any of the functions shown in Table 1. Data polarity is noninverting. Table 1.
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SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001 logic diagram (positive logic) OE DIR CMS CKOE A1 2 1 10 32 3 1D C1 62 PRODUCT PREVIEW CLK B1 1D C1 55 CLK CLKOUT FSTA SYSCLK 31 34 64 33 To Seventeen Other Channels 3–100 VREF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SSCLK
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SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001 Function Tables A-TO-B DIRECTION INPUTS OUTPUTS CKOE OE CMS DIR SYSCLK A SSCLK CLKOUT B L L X L H or L X SYSCLK SYSCLK L L X L ↑ L SYSCLK SYSCLK B0 L L L X L ↑ H SYSCLK SYSCLK H L H X L X X SYSCLK SYSCLK Z H L X L X L Z Z L H L X L X H Z Z H H H X X X X Z Z Z L H H X ↑ X SYSCLK SYSCLK Z L H
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SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† PRODUCT PREVIEW Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): A-port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
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SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001 recommended operating conditions (see Notes 4 through 7) Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK IOH Input clamp current High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate NOM MAX
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SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port and CLKOUT A port and CLKOUT VOL B port and SSCLK MIN VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.15 V IOH = –12 mA IOH = –24 mA TYP† MAX UNIT –1.2 V VCC–0.2 2.
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SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001 hot-insertion specifications for A port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, BIAS VCC = 0, VI or VO = 0 to 5.5 V OE = 0 10 µA VO = 0.5 V to 3 V, ±30 µA IOZPD VCC = 1.5 V to 0, VO = 0.
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SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.
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SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001 skew characteristics over recommended ranges of supply voltage and operating free-air temperature, VREF = 1 V (unless otherwise noted); standard lumped loads, CL = 30 pF for B port (see Figure 1)† FROM (INPUT) TO (OUTPUT) EDGE RATE‡ FSTA tsk(LH)¶ tsk(HL)¶ SYSCLK B Slow – ns tsk(LH)¶ tsk(HL)¶ SYSCLK B Fast – ns SYSCLK SSCLK + ∆ ∆B (see Figure 2) PARAMETER
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SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001 skew characteristics over recommended ranges of supply voltage and operating free-air temperature, VREF = 1 V (unless otherwise noted); standard lumped loads, CL = 30 pF for B port (see Figure 1) (continued)† FROM (INPUT) TO (OUTPUT) tsk(t)¶ SYSCLK B tsk(prLH)# tsk(prHL)# SYSCLK tsk(prLH)# tsk(prHL)# SYSCLK PRODUCT PREVIEW PARAMETER EDGE RATE‡ FSTA TEST CONDITI
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SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V S1 500 Ω Open GND CL = 50 pF (see Note A) 500 Ω 12.5 Ω S1 Open 6V GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V 3V 1.5 V Input 1.5 V Timing Input 1.
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SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001 1.5 V 12.5 Ω From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS A SYSCLK PRODUCT PREVIEW SYSCLK to B tPLH SYSCLK to B tPHL B1 ∆B ∆B B18 SYSCLK to SSCLK FSTA (Fast) SYSCLK to SSCLK FSTA (Fast) SYSCLK to SSCLK FSTA (Slow) SYSCLK to SSCLK FSTA (Slow) SSCLK NOTES: A. B. C. D.
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SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application is probably a distributed load. The physical representation is shown in Figure 3.
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SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001 switching characteristics over recommended operating conditions for the bus transceiver function (unless otherwise noted) (see Figure 4) PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL PRODUCT PREVIEW tPLH tPHL FROM (INPUT) TO (OUTPUT) A B SYSCLK EDGE RATE† FSTA Slow – Fast – Slow – B ns Fast Slow tPLH tPHL Fast – GND SYSCLK SSCLK ns Slow VCC tPLH tPHL Fast
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SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001 D Member of the Texas Instruments D D D D D D D D D D D DGG OR DGV PACKAGE (TOP VIEW) Widebus Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels LVTTL Interfaces Are 5-V Tolerant High-Drive GTLP Outputs (100 mA)
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SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001 description (continued) This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001 functional description The SN74GTLPH1645 is a high-drive (100 mA), 16-bit bus transceiver partitioned as two 8-bit segments and is designed for asynchronous communication between data buses. The device transmits data from the A port to the B port or from the B port to the A port, depending on the logic level at the direction-control (DIR) input.
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SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001 logic diagram (positive logic) 1 1DIR 56 ERC 1A1 15 1OE 55 2 1B1 42 VREF To Seven Other Channels 28 2DIR 29 2OE 2A1 41 16 2B1 To Seven Other Channels Pin numbers shown are for the DGG and DGV packages.
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SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): A port, ERC, and control inputs . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V B port and VREF . . . . . . .
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SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001 recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage MIN NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 VCC VTT 5.5 V VCC 5.
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SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.15 V IOH = –12 mA IOH = –24 mA VCC = 3.15 V to 3.45 V, A port VCC = 3.15 V VOL II TYP† MAX UNIT –1.2 V VCC–0.2 2.
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SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001 live-insertion specifications for B port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, BIAS VCC = 0, VI or VO = 0 to 1.5 V VO = 0.5 V to 1.5 V, OE = 0 10 µA BIAS VCC = 0, ±30 µA IOZPD VCC = 1.5 V to 0, VCC = 0 to 3.15 V BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA BIAS VCC = 3.
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SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω 12.5 Ω From Output Under Test CL = 30 pF (see Note A) S1 Open 6V GND LOAD CIRCUIT FOR A OUTPUTS Test Point LOAD CIRCUIT FOR B OUTPUTS 3V 1.5 V Input 1.
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SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation is shown in Figure 2.
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SN74GTLPH3245 32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES291C – OCTOBER 1999 – REVISED AUGUST 2001 D Member of Texas Instruments’ Widebus+ D D D D D Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels LVTTL Interfaces Are 5-V Tolerant High-Drive GTLP Outputs (100 mA) D LVTTL Outputs (–24 mA/24 mA) D Variable Edge-
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SN74GTLPH3245 32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES291C – OCTOBER 1999 – REVISED AUGUST 2001 description (continued) When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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SN74GTLPH3245 32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES291C – OCTOBER 1999 – REVISED AUGUST 2001 functional description The SN74GTLPH3245 is a high-drive (100 mA), 32-bit bus transceiver partitioned in four 8-bit segments and is designed for asynchronous communication between data buses. The device transmits data from the A port to the B port or from the B port to the A port, depending on the logic level at the direction-control (DIR) input.
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SN74GTLPH3245 32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES291C – OCTOBER 1999 – REVISED AUGUST 2001 logic diagram (positive logic)† 1DIR B3 B4 1ERC 1A1 E1 A4 A3 E6 1OE 1B1 1VREF To Seven Other Channels PRODUCT PREVIEW 2DIR K3 K4 2A1 F5 F2 To Seven Other Channels † 1VCC and 1BIAS VCC are associated with these channels.
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SN74GTLPH3245 32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES291C – OCTOBER 1999 – REVISED AUGUST 2001 logic diagram (positive logic) (continued)† 3DIR L3 L4 2ERC 3A1 R1 K5 K2 R6 3OE 3B1 2VREF To Seven Other Channels W3 W4 4A1 T5 T2 PRODUCT PREVIEW 4DIR 4OE 4B1 To Seven Other Channels † 2VCC and 2BIAS VCC are associated with these channels.
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SN74GTLPH3245 32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES291C – OCTOBER 1999 – REVISED AUGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† PRODUCT PREVIEW Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): A port, ERC, and control inputs . . . . . . . . . . . . . . . . . . . . . –0.
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SN74GTLPH3245 32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES291C – OCTOBER 1999 – REVISED AUGUST 2001 recommended operating conditions (see Notes 4 through 7) Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 VCC VTT 5.5 V VCC 5.5 V B port Except B port B port ERC Except B port and ERC VREF+0.
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SN74GTLPH3245 32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES291C – OCTOBER 1999 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.15 V IOH = –12 mA IOH = –24 mA VCC = 3.15 V to 3.45 V, A port VCC = 3.15 V VOL B port A-port and control inputs II‡ VCC = 3.15 V VCC = 3.
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SN74GTLPH3245 32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES291C – OCTOBER 1999 – REVISED AUGUST 2001 live-insertion specifications for B port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, BIAS VCC = 0, VI or VO = 0 to 1.5 V VO = 0.5 V to 1.5 V, OE = 0 10 µA BIAS VCC = 0, ±30 µA IOZPD VCC = 1.5 V to 0, VCC = 0 to 3.15 V BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA BIAS VCC = 3.
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SN74GTLPH3245 32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES291C – OCTOBER 1999 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω 12.5 Ω From Output Under Test CL = 30 pF (see Note A) S1 Open 6V GND LOAD CIRCUIT FOR A OUTPUTS Test Point LOAD CIRCUIT FOR B OUTPUTS 3V 1.5 V Input 1.
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SN74GTLPH3245 32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES291C – OCTOBER 1999 – REVISED AUGUST 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation is shown in Figure 2.
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SN74GTLPH1655 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES294C – OCTOBER 1999 – REVISED AUGUST 2001 D Member of Texas Instruments’ Widebus D D D D D D D D D D D D D D DGG PACKAGE (TOP VIEW) Family UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Inte
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SN74GTLPH1655 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES294C – OCTOBER 1999 – REVISED AUGUST 2001 description (continued) GTLP is the Texas Instruments (TI) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH1655 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.
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SN74GTLPH1655 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES294C – OCTOBER 1999 – REVISED AUGUST 2001 functional description The SN74GTLPH1655 is a high-drive (100 mA), 16-bit UBT transceiver containing D-type latches and D-type flip-flops for data-path operation in transparent, latched, or clocked modes. The device is uniquely partitioned as two 8-bit transceivers with individual latch timing and output signals and a common clock for both transceiver words.
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SN74GTLPH1655 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES294C – OCTOBER 1999 – REVISED AUGUST 2001 Function Tables (Continued) OUTPUT ENABLE INPUTS OE OEAB L L OUTPUTS OEBA A PORT L L Active B PORT Active† L H Z Active L H L Active Z L H H Z Z H X X Z Z † This condition is not recommended.
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SN74GTLPH1655 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES294C – OCTOBER 1999 – REVISED AUGUST 2001 logic diagram (positive logic) (continued) VREF ERC CLK 2LEAB 2LEBA 2OEBA 2OEAB OE 2A1 41 61 64 35 34 32 31 33 17 1D C1 48 2B1 CLK 1D C1 CLK To Seven Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3–139
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SN74GTLPH1655 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES294C – OCTOBER 1999 – REVISED AUGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): A port, ERC, and control inputs . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V B port and VREF . . . .
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SN74GTLPH1655 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES294C – OCTOBER 1999 – REVISED AUGUST 2001 recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage MIN NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 VCC VTT 5.5 V VCC 5.
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SN74GTLPH1655 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES294C – OCTOBER 1999 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.15 V IOH = –12 mA IOH = –24 mA VCC = 3.15 V to 3.45 V, A port VCC = 3.15 V VOL II TYP† MAX UNIT –1.2 V VCC–0.2 2.
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SN74GTLPH1655 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES294C – OCTOBER 1999 – REVISED AUGUST 2001 live-insertion specifications for B port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, BIAS VCC = 0, VI or VO = 0 to 1.5 V VO = 0.5 V to 1.5 V, OE = 0 10 µA BIAS VCC = 0, ±30 µA IOZPD VCC = 1.5 V to 0, VCC = 0 to 3.15 V BIAS VCC = 0, VO = 0.5 V to 1.
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SN74GTLPH1655 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES294C – OCTOBER 1999 – REVISED AUGUST 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.
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SN74GTLPH1655 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES294C – OCTOBER 1999 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 Ω S1 From Output Under Test Open CL = 50 pF (see Note A) 500 Ω 12.5 Ω S1 Open 6V GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V 3V 1.5 V Input 1.5 V Timing Input 1.
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SN74GTLPH1655 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES294C – OCTOBER 1999 – REVISED AUGUST 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation is shown in Figure 2.
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SN74GTLPH1655 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES294C – OCTOBER 1999 – REVISED AUGUST 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.
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SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 D Member of the Texas Instruments D D D D D D D D D D D D Widebus Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels Split LVTTL Port Provides a Feedback Path for Control
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SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 description (continued) GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLP2033 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.
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SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 ORDERING INFORMATION TA –40°C to 85°C PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP – DGG Tape and reel SN74GTLP2033DGGR GTLP2033 TVSOP – DGV Tape and reel SN74GTLP2033DGVR GT2033 VFBGA – GQL Tape and reel SN74GTLP2033GQLR GR033 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design g
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SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 Function Tables FUNCTION/MODE INPUTS OEBA OEAB OEAB OMODE1 OMODE0 IMODE1 IMODE0 LOOPBACK L L X X X X X X L X H X X X X X X H L L L X X X X H L L H X X X X H L H X X X X H L X X X L L L H X H X X L L L H L X X X L H L H X H X X L H L H L X X X H X L H X H X
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SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 Function Tables (Continued) LOOPBACK Q† LOOPBACK L B port H Point P‡ † Q is the input to the B-to-A logic element. ‡ P is the output of the A-to-B logic element (see functional block diagram).
PAGE 215
SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 functional block diagram VREF 26 42 ERC 44 OEAB OEAB OMODE0 41 24 25 OMODE1 38 CLKAB/LEAB Transceiver 1D C1 46 B1 AI1 2 P 1D C1 IMODE0 48 1 IMODE1 35 CLKBA/LEBA 1D C1 3 AO1 Q 1D OEBA 32 C1 One of Eight Channels LOOPBACK 29 Pin numbers shown are for the DGG and DGV packages.
PAGE 216
SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): AI port, ERC, and control inputs . . . . . . . . . . . . . . . . . . . . .
PAGE 217
SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK IOH Input clamp current High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate
PAGE 218
SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH AO TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.15 V IOH = –12 mA IOH = –24 mA VCC = 3.15 V to 3.45 V, AO VCC = 3.15 V VOL B port II‡ IOZ‡ ICC MIN VCC = 3.
PAGE 219
SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted) MIN fclock tw tsu th 3–158 Clock frequency Pulse duration CLKAB/LEAB or CLKBA/LEBA 2.8 AI before CLKAB↑ 1.1 AI before CLKBA↑ 1.
PAGE 220
SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.
PAGE 221
SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) (continued) PARAMETER FROM (INPUT) TO (OUTPUT) EDGE RATE† tPLH tPHL LOOPBACK AO – tPLH tPHL AI (loopback high) AO – tr Rise time, B-port outputs (20% to 80%) MIN TYP‡ MAX 2.
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SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω 12.5 Ω S1 Open 6V GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V 3V 1.5 V Input 1.5 V Timing Input 1.
PAGE 223
SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application is probably a distributed load. The physical representation is shown in Figure 2.
PAGE 224
SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 switching characteristics over recommended operating conditions for the bus transceiver function (unless otherwise noted) (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) EDGE RATE† tPLH tPHL AI (buffer) B Slow tPLH tPHL AI (buffer) B Fast tPLH tPHL LEAB (latch mode) B Slow tPLH tPHL LEAB (latch mode) B Fast tPLH tPHL CLKAB
PAGE 225
SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001 D Member of the Texas Instruments D D D D D D D D D D D D D Widebus Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels Split LVTTL Port Provides a Feedback Path for Cont
PAGE 226
SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001 description (continued) GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLP22033 is given only at the preferred higher noise margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.
PAGE 227
SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001 ORDERING INFORMATION TA –40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TOP-SIDE MARKING TSSOP – DGG Tape and reel SN74GTLP22033DGGR GTLP22033 TVSOP – DGV Tape and reel SN74GTLP22033DGVR GT22033 VFBGA – GQL Tape and reel SN74GTLP22033GQLR GS033 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB de
PAGE 228
SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001 Function Tables FUNCTION/MODE INPUTS OEBA OEAB OEAB OMODE1 OMODE0 IMODE1 IMODE0 LOOPBACK L L X X X X X X L X H X X X X X X H L L L X X X X H L L H X X X X H L H X X X X H L X X X L L L H X H X X L L L H L X X X L H L H X H X X L H L H L X X X H X L H X H X
PAGE 229
SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001 Function Tables (Continued) LOOPBACK Q† LOOPBACK L B port H Point P‡ † Q is the input to the B-to-A logic element. ‡ P is the output of the A-to-B logic element (see functional block diagram).
PAGE 230
SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001 functional block diagram VREF 26 42 ERC 44 OEAB OEAB OMODE0 41 24 25 OMODE1 38 CLKAB/LEAB Transceiver 1D C1 46 B1 AI1 2 P 1D C1 IMODE0 48 1 IMODE1 35 CLKBA/LEBA 1D C1 3 AO1 Q 1D OEBA 32 C1 One of Eight Channels LOOPBACK 29 Pin numbers shown are for the DGG and DGV packages.
PAGE 231
SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): AI port, ERC, and control inputs . . . . . . . . . . . . . . . . . . . . .
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SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001 recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK IOH Input clamp current High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate
PAGE 233
SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH AO TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.15 V IOH = –6 mA IOH = –12 mA VCC = 3.15 V VOL B port II‡ IOZ‡ ICC TYP† VCC = 3.15 V MAX UNIT –1.2 V VCC–0.
PAGE 234
SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted) MIN fclock tw tsu th 3–174 Clock frequency Pulse duration CLKAB/LEAB or CLKBA/LEBA 2.8 AI before CLKAB↑ 1.1 AI before CLKBA↑ 1.
PAGE 235
SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.
PAGE 236
SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) (continued) PARAMETER FROM (INPUT) TO (OUTPUT) EDGE RATE† tPLH tPHL LOOPBACK AO – tPLH tPHL AI (loopback high) AO – tr Rise time, B-port outputs (20% to 80%) MIN MAX 2.5 6.
PAGE 237
SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω 12.5 Ω S1 Open 6V GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V 3V 1.5 V Input 1.5 V Timing Input 1.
PAGE 238
SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application is probably a distributed load. The physical representation is shown in Figure 2.
PAGE 239
SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001 switching characteristics over recommended operating conditions for the bus transceiver function (unless otherwise noted) (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) EDGE RATE† tPLH tPHL AI (buffer) B Slow tPLH tPHL AI (buffer) B Fast tPLH tPHL LEAB (latch mode) B Slow tPLH tPHL LEAB (latch mode) B Fast tPLH tPHL CLKAB
PAGE 240
SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 D Member of the Texas Instruments D D D D D D D D D D D D Widebus Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels Split LVTTL Port Provides a Feedback Path for Control
PAGE 241
SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 description (continued) GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLP2034 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.
PAGE 242
SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 ORDERING INFORMATION TA –40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TOP-SIDE MARKING TSSOP – DGG Tape and reel SN74GTLP2034DGGR GTLP2034 TVSOP – DGV Tape and reel SN74GTLP2034DGVR GT2034 VFBGA – GQL Tape and reel SN74GTLP2034GQLR GR034 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design g
PAGE 243
SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 Function Tables FUNCTION/MODE INPUTS OEBA OEAB OEAB OMODE1 OMODE0 IMODE1 IMODE0 LOOPBACK L L X X X X X X L X H X X X X X X H L L L X X X X H L L H X X X X H L H X X X X H L X X X L L L H X H X X L L L H L X X X L H L H X H X X L H L H L X X X H X L H X H X
PAGE 244
SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 Function Tables (Continued) LOOPBACK Q† LOOPBACK L B port H Point P‡ † Q is the input to the B-to-A logic element. ‡ P is the output of the A-to-B logic element (see functional block diagram).
PAGE 245
SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 functional block diagram VREF 26 42 ERC 44 OEAB OEAB OMODE0 41 24 25 OMODE1 38 CLKAB/LEAB Transceiver 1D C1 46 B1 AI1 2 P 1D C1 IMODE0 48 1 IMODE1 35 CLKBA/LEBA 1D C1 3 AO1 Q 1D OEBA 32 C1 One of Eight Channels LOOPBACK 29 Pin numbers shown are for the DGG and DGV packages.
PAGE 246
SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): AI port, ERC, and control inputs . . . . . . . . . . . . . . . . . . . . .
PAGE 247
SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK IOH Input clamp current High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate
PAGE 248
SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH AO TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.15 V IOH = –12 mA IOH = –24 mA VCC = 3.15 V to 3.45 V, AO VCC = 3.15 V VOL B port II‡ IOZ‡ ICC MIN VCC = 3.
PAGE 249
SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted) MIN fclock tw tsu th 3–190 Clock frequency Pulse duration Setup time Hold time POST OFFICE BOX 655303 CLKAB/LEAB or CLKBA/LEBA 2.8 AI before CLKAB↑ 1.1 AI before CLKBA↑ 1.
PAGE 250
SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.
PAGE 251
SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) (continued) PARAMETER FROM (INPUT) TO (OUTPUT) EDGE RATE† tPLH tPHL LOOPBACK AO – tPLH tPHL AI (loopback high) AO – tr Rise time, B-port outputs (20% to 80%) MIN MAX 2.5 5.
PAGE 252
SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω 12.5 Ω S1 Open 6V GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V 3V 1.5 V Input 1.5 V Timing Input 1.
PAGE 253
SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application is probably a distributed load. The physical representation is shown in Figure 2.
PAGE 254
SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 switching characteristics over recommended operating conditions for the bus transceiver function (unless otherwise noted) (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) EDGE RATE† tPLH tPHL AI (buffer) B Slow tPLH tPHL AI (buffer) B Fast tPLH tPHL LEAB (latch mode) B Slow tPLH tPHL LEAB (latch mode) B Fast tPLH tPHL CLKAB
PAGE 255
SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001 D Member of the Texas Instruments D D D D D D D D D D D D D Widebus Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels Split LVTTL Port Provides a Feedback Path for Cont
PAGE 256
SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001 description (continued) GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLP22034 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.
PAGE 257
SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001 ORDERING INFORMATION TA –40°C to 85°C PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP – DGG Tape and reel SN74GTLP22034DGGR GTLP22034 TVSOP – DGV Tape and reel SN74GTLP22034DGVR GT22034 VFBGA – GQL Tape and reel SN74GTLP22034GQLR GS034 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB de
PAGE 258
SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001 Function Tables FUNCTION/MODE INPUTS OEBA OEAB OEAB OMODE1 OMODE0 IMODE1 IMODE0 LOOPBACK L L X X X X X X L X H X X X X X X H L L L X X X X H L L H X X X X H L H X X X X H L X X X L L L H X H X X L L L H L X X X L H L H X H X X L H L H L X X X H X L H X H X
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SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001 Function Tables (Continued) LOOPBACK Q† LOOPBACK L B port H Point P‡ † Q is the input to the B-to-A logic element. ‡ P is the output of the A-to-B logic element (see functional block diagram).
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SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001 functional block diagram VREF 26 42 ERC 44 OEAB OEAB OMODE0 41 24 25 OMODE1 38 CLKAB/LEAB Transceiver 1D C1 46 B1 AI1 2 P 1D C1 IMODE0 48 1 IMODE1 35 CLKBA/LEBA 1D C1 3 AO1 Q 1D OEBA 32 C1 One of Eight Channels LOOPBACK 29 Pin numbers shown are for the DGG and DGV packages.
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SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): AI port, ERC, and control inputs . . . . . . . . . . . . . . . . . . . . .
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SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001 recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK IOH Input clamp current High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate
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SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH AO VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.15 V IOH = –6 mA IOH = –12 mA VCC = 3.15 V VOL B port II‡ IOZ‡ ICC TYP† VCC = 3.15 V MAX UNIT –1.
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SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted) MIN fclock tw tsu th 3–206 Clock frequency Pulse duration Setup time Hold time POST OFFICE BOX 655303 CLKAB/LEAB or CLKBA/LEBA 2.8 AI before CLKAB↑ 1.1 AI before CLKBA↑ 1.
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SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.
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SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) (continued) PARAMETER FROM (INPUT) TO (OUTPUT) EDGE RATE† tPLH tPHL LOOPBACK AO – tPLH tPHL AI (loopback high) AO – tr Rise time, B-port outputs (20% to 80%) MIN MAX 2.5 6.
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SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω 12.5 Ω S1 Open 6V GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V 3V 1.5 V Input 1.5 V Timing Input 1.
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SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application is probably a distributed load. The physical representation is shown in Figure 2.
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SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001 switching characteristics over recommended operating conditions for the bus transceiver function (unless otherwise noted) (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) EDGE RATE† tPLH tPHL AI (buffer) B Slow tPLH tPHL AI (buffer) B Fast tPLH tPHL LEAB (latch mode) B Slow tPLH tPHL LEAB (latch mode) B Fast tPLH tPHL CLKAB
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SN74GTLPH16612 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES326C – MARCH 2000 – REVISED AUGUST 2001 D Member of Texas Instruments’ Widebus D D D D D D D D D D D D Family UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels LVTTL Interfaces are 5-V Tolerant Medium-Dr
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SN74GTLPH16612 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES326C – MARCH 2000 – REVISED AUGUST 2001 description (continued) VCC (5 V) supplies the internal and GTLP circuitry, while VCC (3.3 V) supplies the LVTTL output buffers. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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SN74GTLPH16612 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES326C – MARCH 2000 – REVISED AUGUST 2001 FUNCTION TABLE† INPUTS CEAB OEAB LEAB X H L L L OUTPUT B MODE X Z Isolation X B0‡ B0§ Latched storage of A data CLKAB A X X L H L L L X X L H X L L X L H X H H L L L ↑ L L L L L ↑ H H B0§ True transparent Clocked storage of A data H L L X X Clock inhibit † A-to-B data flow is shown. B-to-A data flow is similar, but uses CEBA, OEBA, LEBA, and CLKBA.
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SN74GTLPH16612 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES326C – MARCH 2000 – REVISED AUGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC: 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
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SN74GTLPH16612 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES326C – MARCH 2000 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH A port TEST CONDITIONS VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V, VCC (3.3 V) = 3.15 V to 3.45 V, VCC (5 V) = 4.75 V to 5.25 V VCC (3.3 V) = 3.15 V, VOL II A port IOZL ICC (3.3 V) ICC (5 V) Cio VCC (5 V) = 4.75 V IOH = –100 µA VCC (3.3 V) –0.
PAGE 275
SN74GTLPH16612 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES326C – MARCH 2000 – REVISED AUGUST 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted) (see Figure 1) MIN fclock Clock frequency tw Pulse duration tsu th Setup time Hold time LEAB or LEBA high 3.3 CLKAB or CLKBA high or low 5.7 A before CLKAB↑ 1 B before CLKBA↑ 1.8 A before LEAB↓ 0.5 B before LEBA↓ 1.
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SN74GTLPH16612 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES326C – MARCH 2000 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION VTT 6V 500 Ω From Output Under Test S1 Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND CL = 50 pF (see Note A) 500 Ω 25 Ω S1 Open 6V GND From Output Under Test CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V Input 3V Timing Input 1.5 V 0V 1.5 V 1.5 V tsu 0V VOLTAGE WAVEFORMS PULSE DURATION 3V Input Test Point 1.
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SN74GTLPH16612 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES326C – MARCH 2000 – REVISED AUGUST 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The previous switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation is shown in Figure 2.
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SN74GTLPH16912 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES288C – OCTOBER 1999 – REVISED JULY 2001 D Member of Texas Instruments’ Widebus D D D D D D D D D D D D D DGG OR DGV PACKAGE (TOP VIEW) Family UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, and Clock-Enabled Modes TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Inter
PAGE 279
SN74GTLPH16912 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES288C – OCTOBER 1999 – REVISED JULY 2001 description (continued) Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage. This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC.
PAGE 280
SN74GTLPH16912 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES288C – OCTOBER 1999 – REVISED JULY 2001 functional description The SN74GTLPH16912 is a medium-drive (50 mA), 18-bit UBT transceiver containing D-type latches and D-type flip-flops for data-path operation in transparent, latched, clocked, or clock-enabled modes and can replace any of the functions shown in Table 1. Data polarity is noninverting. Table 1.
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SN74GTLPH16912 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES288C – OCTOBER 1999 – REVISED JULY 2001 logic diagram (positive logic) 35 VREF 1 OEAB CEAB 56 55 CLKAB 2 LEAB 28 LEBA 30 CLKBA CEBA 29 27 OEBA CE 1D 3 A1 C1 CLK CE 1D C1 CLK To 17 Other Channels 3–224 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 54 B1
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SN74GTLPH16912 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES288C – OCTOBER 1999 – REVISED JULY 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): A-port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V B port and VREF . . . . . . . . . . . .
PAGE 283
SN74GTLPH16912 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES288C – OCTOBER 1999 – REVISED JULY 2001 recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK IOH Input clamp current Low-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.
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SN74GTLPH16912 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES288C – OCTOBER 1999 – REVISED JULY 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.
PAGE 285
SN74GTLPH16912 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES288C – OCTOBER 1999 – REVISED JULY 2001 live-insertion specifications for B port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, BIAS VCC = 0, VI or VO = 0 to 1.5 V VO = 0.5 V to 1.5 V, OE = 0 10 µA BIAS VCC = 0, ±30 µA IOZPD VCC = 1.5 V to 0, VCC = 0 to 3.15 V BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA BIAS VCC = 3.15 V to 3.
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SN74GTLPH16912 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES288C – OCTOBER 1999 – REVISED JULY 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL ten tdis tr tf tPLH FROM (INPUT) TO (OUTPUT) A B LEAB B CLKAB B OEAB B 2.1 6 2.2 6.3 2.2 6.3 2.2 6.5 2.2 6.5 2 6.5 2 6.
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SN74GTLPH16912 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES288C – OCTOBER 1999 – REVISED JULY 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 Ω From Output Under Test S1 CL = 50 pF (see Note A) 25 Ω Open S1 Open 6V GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND 500 Ω From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V 3V 1.5 V Input 1.5 V Timing Input 1.
PAGE 288
SN74GTLPH16912 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES288C – OCTOBER 1999 – REVISED JULY 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation is shown in Figure 2.
PAGE 289
SN74GTLPH16916 17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES347B – JANUARY 2001 – REVISED AUGUST 2001 D Member of Texas Instruments’ Widebus D D D D D D D D D D D D D D DGG OR DGV PACKAGE (TOP VIEW) Family UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, and Clock-Enabled Mode TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic I
PAGE 290
SN74GTLPH16916 17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES347B – JANUARY 2001 – REVISED AUGUST 2001 description (continued) GTLP is the Texas Instruments (TI) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH16916 is given only at the preferred higher noise margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.
PAGE 291
SN74GTLPH16916 17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES347B – JANUARY 2001 – REVISED AUGUST 2001 functional description The SN74GTLPH16916 is a medium-drive (50 mA), 17-bit UBT transceiver containing D-type latches and D-type flip-flops for data-path operation in transparent, latched, clocked, or clock-enabled modes and can replace any of the functions shown in Table 1. Data polarity is noninverting. Table 1.
PAGE 292
SN74GTLPH16916 17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES347B – JANUARY 2001 – REVISED AUGUST 2001 Function Tables OUTPUT ENABLE† INPUTS CEAB OEAB LEAB X H L L L OUTPUT B MODE X Z Isolation X B0‡ B0§ Latched storage of A data CLKAB A X X L H L L L X X L H X L L X L H X H H L L L ↑ L L L L L ↑ H H B0§ True transparent Clocked storage of A data H L L X X Clock inhibit † A-to-B data flow is shown.
PAGE 293
SN74GTLPH16916 17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES347B – JANUARY 2001 – REVISED AUGUST 2001 logic diagram (positive logic) VREF OEAB CEAB CLKAB LEAB LEBA CLKBA CEBA OEBA A1 35 1 56 55 2 28 30 29 27 CE 1D 3 CE 1D C1 CLK 54 C1 CLK B1 1 of 17 Channels 31 CLKIN CLKOUT 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3–237
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SN74GTLPH16916 17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES347B – JANUARY 2001 – REVISED AUGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): A port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 295
SN74GTLPH16916 17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES347B – JANUARY 2001 – REVISED AUGUST 2001 recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK IOH Input clamp current Low-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate NOM MAX UNIT 3.15 3.
PAGE 296
SN74GTLPH16916 17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES347B – JANUARY 2001 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.
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SN74GTLPH16916 17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES347B – JANUARY 2001 – REVISED AUGUST 2001 live-insertion specifications for B port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, BIAS VCC = 0, VI or VO = 0 to 1.5 V VO = 0.5 V to 1.5 V, OE = 0 10 µA BIAS VCC = 0, ±30 µA IOZPD VCC = 1.5 V to 0, VCC = 0 to 3.15 V BIAS VCC = 0, VO = 0.5 V to 1.
PAGE 298
SN74GTLPH16916 17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES347B – JANUARY 2001 – REVISED AUGUST 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.
PAGE 299
SN74GTLPH16916 17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES347B – JANUARY 2001 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 Ω From Output Under Test S1 Open CL = 50 pF (see Note A) 500 Ω 25 Ω S1 Open 6V GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V 3V 1.5 V Input 1.5 V Timing Input 1.
PAGE 300
SN74GTLPH16916 17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES347B – JANUARY 2001 – REVISED AUGUST 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation is shown in Figure 2.
PAGE 301
SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES292C – OCTOBER 1999 – REVISED SEPTEMBER 2001 D Member of the Texas Instruments D D D D D D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels LVTTL Interfaces Are 5-V Tolerant Medium-Drive GTLP Outputs (50 mA) LVTTL Outputs
PAGE 302
SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES292C – OCTOBER 1999 – REVISED SEPTEMBER 2001 description (continued) This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
PAGE 303
SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES292C – OCTOBER 1999 – REVISED SEPTEMBER 2001 functional description The SN74GTLPH16945 is a medium-drive (50 mA), 16-bit bus transceiver partitioned as two 8-bit segments and is designed for asynchronous communication between data buses. The device transmits data from the A port to the B port or from the B port to the A port, depending on the logic level at the direction-control (DIR) input.
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SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES292C – OCTOBER 1999 – REVISED SEPTEMBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): A port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V B port and VREF . . . . . . . . . . . . . .
PAGE 305
SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES292C – OCTOBER 1999 – REVISED SEPTEMBER 2001 recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK IOH Input clamp current Low-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.
PAGE 306
SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES292C – OCTOBER 1999 – REVISED SEPTEMBER 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.15 V IOH = –12 mA IOH = –24 mA VOL B port II Control inputs A port IOZH‡ B port TYP† MAX UNIT –1.2 V VCC–0.2 2.4 V 2 IOL = 100 µA IOL = 12 mA 0.2 0.5 VCC = 3.
PAGE 307
SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES292C – OCTOBER 1999 – REVISED SEPTEMBER 2001 live-insertion specifications for B port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, BIAS VCC = 0, VI or VO = 0 to 1.5 V VO = 0.5 V to 1.5 V, OE = 0 10 µA BIAS VCC = 0, ±30 µA IOZPD VCC = 1.5 V to 0, VCC = 0 to 3.15 V BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA BIAS VCC = 3.15 V to 3.
PAGE 308
SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES292C – OCTOBER 1999 – REVISED SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω 25 Ω From Output Under Test CL = 30 pF (see Note A) S1 Open 6V GND LOAD CIRCUIT FOR A OUTPUTS Test Point LOAD CIRCUIT FOR B OUTPUTS 3V 1.5 V Input 1.
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SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES292C – OCTOBER 1999 – REVISED SEPTEMBER 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation is shown in Figure 2.
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SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES293B – OCTOBER 1999 – REVISED AUGUST 2001 D Member of Texas Instruments’ Widebus+ D D D D D Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels LVTTL Interfaces Are 5-V Tolerant Medium-Drive GTLP Outputs (50 mA) D LVTTL Outputs (–24 mA/24 mA) D GTLP Rise and Fall Times Designed
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SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES293B – OCTOBER 1999 – REVISED AUGUST 2001 GKE PACKAGE (TOP VIEW) 1 2 3 4 5 terminal assignments 6 1 2 3 4 5 6 A A 1A2 1A1 1DIR 1OE 1B1 1B2 B B 1A4 1A3 GND GND 1B3 1B4 C C 1A6 1A5 1BIAS VCC 1B5 1B6 D D 1A8 1A7 1VCC GND GND 1B7 1B8 E 2A2 2A1 GND GND 2B1 2B2 F 2A4 2A3 2B4 2A6 2A5 1VREF GND 2B3 G 1VCC GND 2B5 2B6 H 2A7 2A8 2DIR 2OE 2B8 2B7 J 3A2 3A1 3DIR 3OE 3B1 3B2 E F G H PRODUC
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SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES293B – OCTOBER 1999 – REVISED AUGUST 2001 logic diagram (positive logic)† 1DIR A3 A4 1A1 A5 A2 F4 1OE 1B1 1VREF To Seven Other Channels H3 H4 2A1 E5 E2 PRODUCT PREVIEW 2DIR 2OE 2B1 To Seven Other Channels † 1VCC and 1BIAS VCC are associated with these channels.
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SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES293B – OCTOBER 1999 – REVISED AUGUST 2001 logic diagram (positive logic) (continued)† 3DIR J3 J4 3A1 J5 J2 P4 3OE 3B1 2VREF To Seven Other Channels PRODUCT PREVIEW 4DIR T3 T4 4A1 N5 N2 To Seven Other Channels † 2VCC and 2BIAS VCC are associated with these channels.
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SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES293B – OCTOBER 1999 – REVISED AUGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
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SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES293B – OCTOBER 1999 – REVISED AUGUST 2001 PRODUCT PREVIEW recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK IOH Input clamp current Low-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.
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SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES293B – OCTOBER 1999 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) VIK VOH A port TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3.
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SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES293B – OCTOBER 1999 – REVISED AUGUST 2001 live-insertion specifications for B port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, BIAS VCC = 0, VI or VO = 0 to 1.5 V VO = 0.5 V to 1.5 V, OE = 0 10 µA BIAS VCC = 0, ±30 µA IOZPD VCC = 1.5 V to 0, VCC = 0 to 3.15 V BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA BIAS VCC = 3.15 V to 3.
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SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES293B – OCTOBER 1999 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω 25 Ω From Output Under Test CL = 30 pF (see Note A) S1 Open 6V GND LOAD CIRCUIT FOR A OUTPUTS Test Point LOAD CIRCUIT FOR B OUTPUTS 3V 1.5 V Input 1.
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SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES293B – OCTOBER 1999 – REVISED AUGUST 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation is shown in Figure 2.
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General Information GTL GTLP ETL BTL/FB+ VME Application Reports Mechanical Data 4–1
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Contents Page SN74ABTE16245 16-Bit Incident-Wave Switching Bus Transceiver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 SN74ABTE16246 11-Bit Incident-Wave Switching Bus Transceiver With 3-State and Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SN74ABTE16245 16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCBS226H – JULY 1993 – REVISED JUNE 2001 D Member of Texas Instruments’ Widebus D D D D D D D D DGG OR DL PACKAGE (TOP VIEW) Family Supports the VME64 ETL Specification Reduced, TTL-Compatible, Input Threshold Range High-Drive Outputs (IOH = –60 mA, IOL = 90 mA) Support 25-Ω Incident-Wave Switching VCCBIAS Pin Minimizes Signal Distortion During Live Insertion Internal Pullup Resistor on OE Keeps Outputs in High-Impedance S
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SN74ABTE16245 16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCBS226H – JULY 1993 – REVISED JUNE 2001 ORDERING INFORMATION –40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA SSOP – DL Tube SN74ABTE16245DL Tape and reel SN74ABTE16245DLR TOP-SIDE MARKING ABTE16245 TSSOP – DGG Tape and reel SN74ABTE16245DGGR ABTE16245 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
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SN74ABTE16245 16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCBS226H – JULY 1993 – REVISED JUNE 2001 recommended operating conditions (see Note 3) VCC Supply voltage VIH High level input voltage High-level VIL Low level input voltage Low-level VI Input voltage IOH High level output current High-level IOL Low level output current Low-level ∆t/∆v Input transition rise or fall rate OE Except OE MIN NOM MAX 4.5 5 5.5 2 V V 1.6 OE 0.8 Except OE 1.
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SN74ABTE16245 16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCBS226H – JULY 1993 – REVISED JUNE 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK B port VOH TEST CONDITIONS VCC = 4.5 V, VCC = 5.5 V, II = –18 mA IOH = –100 µA VCC = 4 4.5 5V IOH = –1 mA IOH = –12 mA VCC = 5.5 V, A port VCC = 4 4.5 5V B port VCC = 4 4.5 5V A port VCC = 4 4.
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SN74ABTE16245 16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCBS226H – JULY 1993 – REVISED JUNE 2001 live-insertion specifications over recommended operating free-air temperature range PARAMETER TEST CONDITIONS ICC (VCCBIAS) VCC = 0 to 4.5 V, VCC = 4.5 V to 5.5 V‡, VCCBIAS = 4.5 V to 5.5 V, VCCBIAS = 4.5 V to 5.5 V, VO A port VCC = 0 VCCBIAS = 4.5 V to 5.5 V VCCBIAS = 4.75 V to 5.25 V IO A port VCC = 0 0, VCCBIAS = 4 4.
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SN74ABTE16245 16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCBS226H – JULY 1993 – REVISED JUNE 2001 extended switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 2) PARAMETER VCC = 5 V, TA = 25°C FROM (INPUT) TO (OUTPUT) LOAD B A RX = 13 Ω B A RX = 26 Ω B A RX = 56 Ω B A RX = Open A B B A B A A B B A RX = 26 Ω 0.5 1 B A RX = 26 Ω 0.5 0.8 1.5 0.5 1.
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SN74ABTE16245 16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCBS226H – JULY 1993 – REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION Device 1 A Y1 A B Y2 Yn Device 1 – Y1 tPLH1 tPHL1 tsk(o) tsk(load) In Device n Device 1 – Yn tsk(temp) Y1 tPLH2 Device n – Yn B Y2 Yn NOTES: A. Pulse skew, tsk(p), is defined as the difference in propagation-delay times tPLH1 and tPHL1 on the same terminal at identical operating conditions. B.
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SN74ABTE16245 16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCBS226H – JULY 1993 – REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION 7V S2 500 Ω 3.
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SN74ABTE16246 11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS SCBS227G – JULY 1993 – REVISED JUNE 2001 D Member of Texas Instruments’ Widebus D D D D D D D D DGG OR DL PACKAGE (TOP VIEW) Family Supports the VME64 ETL Specification Reduced TTL-Compatible Input Threshold Range High-Drive Outputs (IOH = –60 mA, IOL = 90 mA) Support Equivalent 25-Ω Incident-Wave Switching VCCBIAS Pin Minimizes Signal Distortion During Live Insertion Internal Pullup Resistor on OE Keeps
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SN74ABTE16246 11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS SCBS227G – JULY 1993 – REVISED JUNE 2001 FUNCTION TABLE INPUTS OPERATION OE 9DIR 10DIR 11DIR 11OE H X X X X Isolation X 1BI–8BI data to 1A–8A bus (OC†), 1A–8A data to 1BO–8BO bus L X X X L L X X X 9A data to 9B bus L H X X X 9B data to 9A bus L X L X X 10A data to 10B bus L X H X X 10B data to 10A bus L X X L L 11A data to 11B bus L X X L H 11A, 11B isol
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SN74ABTE16246 11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS SCBS227G – JULY 1993 – REVISED JUNE 2001 logic diagram (positive logic) 11OE 11DIR 11B 1 2 3 47 OE 10DIR 10B 25 46 5 44 9DIR 9B 1BO 10A 41 6 43 1BI 11A 26 24 9A 1A 23 To Seven Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–13
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SN74ABTE16246 11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS SCBS227G – JULY 1993 – REVISED JUNE 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SN74ABTE16246 11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS SCBS227G – JULY 1993 – REVISED JUNE 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK B port VOH VCC = 4.5 V, VCC = 5.5 V, II = –18 mA IOH = –100 µA VCC = 4 4.5 5V IOH = –1 mA IOH = –12 mA VCC = 5.5 V, 9A–11A IOH TEST CONDITIONS 1A–8A B port VCC = 4 4.5 5V VCC = 4.5 V, IOH = –64 mA VOH = 5.5 V II IOZH‡ IOZL‡ IO UNIT –1.
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SN74ABTE16246 11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS SCBS227G – JULY 1993 – REVISED JUNE 2001 live-insertion specifications over recommended operating free-air temperature range PARAMETER TEST CONDITIONS ICC (VCCBIAS) VCC = 0 to 4.5 V, VCC = 4.5 V to 5.5 V‡, VCCBIAS = 4.5 V to 5.5 V, VCCBIAS = 4.5 V to 5.5 V, VO A port VCC = 0 VCCBIAS = 4.5 V to 5.5 V VCCBIAS = 4.75 V to 5.25 V IO A port VCC = 0 0, VCCBIAS = 4 4.
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SN74ABTE16246 11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS SCBS227G – JULY 1993 – REVISED JUNE 2001 extended switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 2) PARAMETER tPLH FROM (INPUT) TO (OUTPUT) LOAD 9B 11B 9B–11B 9A 11A 9A–11A RX = 13 Ω 1B–8B 1A–8A RX = 13 Ω tPHL tPHL tPLH tPLH MAX 4 1.5 4.8 3.8 4.7 1.5 5.6 1.5 3.3 4.2 1.5 4.8 1.
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SN74ABTE16246 11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS SCBS227G – JULY 1993 – REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION Device 1 A Y1 A B Y2 Yn Device 1 – Y1 tPLH1 tPHL1 tsk(o) tsk(load) In Device n Device 1 – Yn tsk(temp) Y1 tPLH2 Device n – Yn B Y2 Yn NOTES: A. Pulse skew, tsk(p), is defined as the difference in propagation-delay times tPLH1 and tPHL1 on the same terminal at identical operating conditions. B.
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SN74ABTE16246 11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS SCBS227G – JULY 1993 – REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION 7V Open S2 3.
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General Information GTL GTLP ETL BTL/FB+ VME Application Reports Mechanical Data 5–1
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Contents SN74FB1650 BTL/FB+ 5–2 Page 18-Bit TTL/BTL Universal Storage Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3 SN74FB1651 17-Bit TTL/BTL Universal Storage Transceiver With Buffered Clock Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11 SN74FB1653 17-Bit LVTTL/BTL Universal Storage Transceiver With Buffered Clock Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SN74FB1650 18-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER SCBS178N – AUGUST 1992 – REVISED JUNE 2001 D Compatible With IEEE Std 1194.
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SN74FB1650 18-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER SCBS178N – AUGUST 1992 – REVISED JUNE 2001 description The SN74FB1650 contains two 9-bit transceivers designed to translate signals between TTL and backplane transceiver-logic (BTL) environments. The device is designed specifically to be compatible with IEEE Std 1194.1-1991. The B port operates at BTL-signal levels. The open-collector B ports are specified to sink 100 mA. Two output enables (OEB and OEB) are provided for the B outputs.
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SN74FB1650 18-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER SCBS178N – AUGUST 1992 – REVISED JUNE 2001 functional block diagram 81 1OEB 1OEB 1CLKAB 1LEAB 1LEBA 1CLKBA 1OEA 1OEA 80 83 82 85 84 87 86 90 1AI1 1D C2 76 1B1 C1 89 1AO1 1D C2 C1 To Eight Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC, BIAS VCC, BG VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 344
SN74FB1650 18-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER SCBS178N – AUGUST 1992 – REVISED JUNE 2001 recommended operating conditions (see Note 2) VCC, BG VCC, BIAS VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage IIK IOH Input clamp current IOL B port Except B port B port MIN NOM MAX 4.5 5 5.5 1.62 2.3 2 0.75 1.47 Except B port High-level output current Low-level output current 0.
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SN74FB1650 18-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER SCBS178N – AUGUST 1992 – REVISED JUNE 2001 live-insertion specifications over recommended operating free-air temperature range PARAMETER ICC (BIAS VCC) TEST CONDITIONS VCC = 0 to 4.5 V VCC = 4.5 V to 5.5 V VB = 0 to 2 V, MIN 450 VI (BIAS VCC) = 4.5 V to 5.5 V VO B port VCC = 0, VCC = 0 , VI (BIAS VCC) = 5 V VB = 1 V, IO B port VCC = 0 to 5.5 V, VCC = 0 to 2.2 V, MAX 10 1.62 UNIT µ µA 2.1 V OEB = 0 to 0.
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SN74FB1650 18-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER SCBS178N – AUGUST 1992 – REVISED JUNE 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ tsk(p)† tsk(o)† tt Transition time FROM (INPUT) TO (OUTPUT) MIN TYP MIN AI B LEAB B CLKAB B B AO LEBA AO CLKBA AO OE
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SN74FB1650 18-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER SCBS178N – AUGUST 1992 – REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION 2.1 V 16.5 Ω 7V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) Test Point From Output Under Test CL = 30 pF (see Note A) 500 Ω LOAD CIRCUIT FOR A OUTPUTS TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT FOR B OUTPUTS tw 3V Input 1.5 V 1.5 V 3V 1.
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SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177N – OCTOBER 1993 – REVISED JUNE 2001 D Compatible With IEEE Std 1194.
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SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177N – OCTOBER 1993 – REVISED JUNE 2001 description The SN74FB1651 contains an 8-bit and 9-bit transceiver with a buffered clock. The clock and the transceivers are designed to translate signals between TTL and backplane transceiver-logic (BTL) environments. The device is designed specifically to be compatible with IEEE Std 1194.1-1991. The B port operates at BTL-signal levels.
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SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177N – OCTOBER 1993 – REVISED JUNE 2001 functional block diagram 81 1OEB 80 1OEB 1CLKAB 1LEAB 1LEBA 1CLKBA 1OEA 1OEA 1AI1 83 82 85 84 87 86 Transceiver 90 1D C2 76 1B1 C1 89 1AO1 1D C2 C1 To Eight Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5–13
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SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177N – OCTOBER 1993 – REVISED JUNE 2001 functional block diagram (continued) 45 2OEB 2OEB 2CLKAB 2LEAB 2LEBA 2CLKBA 2OEA 2OEA 46 43 44 41 42 39 40 62 Delay 2CLK 14 2CLKAB Delay Transceiver 2AI2 17 1D C2 C1 2AO2 16 1D C2 C1 To Seven Other Channels 5–14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 60 2B2
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SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177N – OCTOBER 1993 – REVISED JUNE 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC, BIAS VCC, BG VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V B port .
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SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177N – OCTOBER 1993 – REVISED JUNE 2001 electrical characteristics over recommended operating free-air temperature range PARAMETER VIK VOH B port II IIH‡ IIL‡ II = –18 mA II = –40 mA VCC = 4.5 V, VCC = 4.5 V, IOH = –3 mA IOL = 24 mA 2.5 VCC = 4.5 V 0.75 B port IOL = 80 mA IOL = 100 mA Except B port VCC = 5.5 V, VCC = 5.5 V, VI = 5.5 V VI = 2.7 V VCC = 5.5 V, VCC = 5.5 V, VI = 0.5 V VI = 0.75 V VCC = 5.
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SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177N – OCTOBER 1993 – REVISED JUNE 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C MIN fclock tw Clock frequency 150 Pulse duration tsu Setup time th Hold time MIN POST OFFICE BOX 655303 CLK or LE 3.3 3.3 Data before LE 4.8 4.8 Data before CLK↑ 4.9 4.6 Data after LE 1.8 1.
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SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177N – OCTOBER 1993 – REVISED JUNE 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ tsk(p)† tsk(o)† tt Transition time FROM (INPUT) TO (OUTPUT) MIN TYP MIN AI B LEA
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SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177N – OCTOBER 1993 – REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION 2.1 V 16.5 Ω 7V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) Test Point From Output Under Test CL = 30 pF (see Note A) 500 Ω LOAD CIRCUIT FOR A OUTPUTS TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT FOR B OUTPUTS tw 3V 1.5 V Input 1.5 V 3V 1.
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SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702E – AUGUST 1997 – REVISED JUNE 2001 D Compatible With IEEE Std 1194.
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SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702E – AUGUST 1997 – REVISED JUNE 2001 description The SN74FB1653 contains an 8-bit and a 9-bit transceiver with a buffered clock. The clock and transceivers are designed to translate signals between LVTTL and BTL environments. The device is designed specifically to be compatible with IEEE Std 1194.1-1991 (BTL). The A port operates at LVTTL signal levels.
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SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702E – AUGUST 1997 – REVISED JUNE 2001 functional block diagram 1OEB 1OEB 1CLKAB 1LEAB 1LEBA 1CLKBA 1OEA 1OEA 1AI1 81 80 83 82 85 84 87 86 90 1D C2 76 1B1 C1 1D 1AO1 89 C2 C1 To Eight Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5–23
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SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702E – AUGUST 1997 – REVISED JUNE 2001 functional block diagram (continued) 2OEB 2OEB 2CLKAB 2LEAB 2LEBA 2CLKBA 2OEA 2OEA 2SEL2 2SEL1 2CLK 2AI2 45 46 43 44 41 42 39 Delay3 40 M U X 63 Delay2 62 14 M U X 17 Delay1 1D 60 C2 C1 2AO2 1D 16 C2 C1 To Seven Other Channels MUX-MODE DELAY DELAY PATH† INPUTS 2SEL1 2SEL2 2CLKAB TO 2CLKAB 2CLKAB TO 2CLK L L No delay No delay L H No delay Delay
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SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702E – AUGUST 1997 – REVISED JUNE 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range: VCC(5 V), BIAS VCC, BG VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V VCC(3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
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SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702E – AUGUST 1997 – REVISED JUNE 2001 electrical characteristics over recommended operating free-air temperature range PARAMETER MIN TYP† MAX II = –18 mA II = –40 mA AO port VCC(5 V) = 4.5 V, VCC(3.3 V) = 3 V IOH = –3 mA AO port VCC(5 V) = 4.5 V, VCC(3.3 V) = 3 V IOL = 24 mA B port VCC(5 V) = 4.5 V, VCC(3.3 V) = 3 V IOL = 80 mA IOL = 100 mA II Except B port VCC(5 V) = 5.5 V, VCC(3.3 V) = 3.6 V VI = 5.
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SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702E – AUGUST 1997 – REVISED JUNE 2001 live-insertion specifications over recommended operating free-air temperature range PARAMETER ICC (BIAS VCC) VO IO B port B port TEST CONDITIONS VCC(5 V) = 0 to 4.5 V, VCC(3.3 V) = 3.3 V MAX UNIT 450 VCC(5 V) = 4.5 V to 5.5 V, VCC(3.3 V) = 3.3 V VB = 0 to 2 V, µ µA VI (BIAS VCC) = 4.5 V to 5.5 V 10 VCC(5 V) = 0, VCC(3.
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SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702E – AUGUST 1997 – REVISED JUNE 2001 switching characteristics over recommended operating free-air temperature range, VCC(5 V) = 5 V ± 0.5 V and VCC(3.3 V) = 3.
PAGE 365
SN74FB1653 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS702E – AUGUST 1997 – REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION 2.1 V 500 Ω From Output Under Test 6V Open S1 GND CL = 50 pF (see Note A) 16.5 Ω From Output Under Test 500 Ω S1 Open 6V GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V 1.5 V Input 3V 1.5 V Timing Input 1.
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SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176N – NOVEMBER 1991 – REVISED JUNE 2001 D Compatible With IEEE Std 1194.
PAGE 367
SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176N – NOVEMBER 1991 – REVISED JUNE 2001 description (continued) BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected. BG VCC and BG GND are the supply inputs for the bias generator.
PAGE 368
SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176N – NOVEMBER 1991 – REVISED JUNE 2001 functional block diagram 18 LCA 20 SEL0 15 SEL1 16 LCB OEB OEB OEA 46 45 47 1D C1 40 1D C1 A1 MUX B1 50 MUX 1D C1 1D C1 To Eight Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
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SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176N – NOVEMBER 1991 – REVISED JUNE 2001 recommended operating conditions (see Note 2) VCC, BIAS VCC, BG VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage IOH High-level output current IOL Low-level output current B port Except B port B port MIN NOM MAX 4.5 5 5.5 1.62 2.3 2 0.75 1.47 Except B port 0.
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SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176N – NOVEMBER 1991 – REVISED JUNE 2001 live-insertion specifications over recommended operating free-air temperature range PARAMETER ICC (BIAS VCC) TEST CONDITIONS VCC = 0 to 4.5 V VCC = 4.5 V to 5.5 V VB = 0 to 2 V, MIN 450 VI (BIAS VCC) = 4.5 V to 5.5 V VO B port VCC = 0, VCC = 0, VI (BIAS VCC) = 5 V VB = 1 V, IO B port VCC = 0 to 5.5 V, VCC = 0 to 2.2 V, MAX 10 1.62 UNIT µ µA 2.1 V OEB = 0 to 0.
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SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176N – NOVEMBER 1991 – REVISED JUNE 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH TO (OUTPUT) VCC = 5 V, TA = 25°C MIN TYP 4.5 5.9 3.2 6.6 2.9 4 5.7 2.6 5.9 4.1 5 6.5 3.6 7.3 3.3 4.5 6.1 3 6.5 4.5 5.4 7 3.9 7.8 4 5.1 6.7 3.4 7.4 2.8 3.7 4.7 1.9 6 2.5 3.4 4.9 1.8 5.5 2.5 3.8 5.3 1.9 6.
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SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176N – NOVEMBER 1991 – REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION 2.1 V 16.5 Ω 7V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) Test Point From Output Under Test CL = 30 pF (see Note A) 500 Ω LOAD CIRCUIT FOR A OUTPUTS TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT FOR B OUTPUTS tw 3V Input 1.5 V 1.5 V 3V 1.5 V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION tsu th 3V 3V Input 1.
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SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 D Compatible With IEEE Std 1194.
PAGE 374
SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 description (continued) Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the LOOPBACK input. When LOOPBACK is low, B-port data is the B-to-A input. When LOOPBACK is high, the output of the selected A-to-B logic element (prior to inversion) is the B-to-A input. The AO port-enable/-disable control is provided by OEA.
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SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 Function Tables FUNCTION/MODE INPUTS OEA OEB OEB OMODE1 OMODE0 IMODE1 IMODE0 LOOPBACK FUNCTION/MODE L L X X X X X X L X H X X X X X X H L L L X X X AI to B, buffer mode X H L L H X X X AI to B, flip-flop mode X H L H X X X X AI to B, latch mode H L X X X L L L H X H X X L L L H L X X X L H L H X H X X L H L H L X X X H X
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SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 Function Tables (Continued) LOOPBACK Q† LOOPBACK L B port H Point P‡ † Q is the input to the B-to-A logic element. ‡ P is the output of the A-to-B logic element (see functional block diagram).
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SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 functional block diagram 23 OEB OEB OMODE1 24 21 20 OMODE0 47 CLKAB/ LEAB Transceiver 1D C1 40 AI1 B1 50 P 1D C1 IMODE1 46 45 IMODE0 19 CLKBA/ LEBA 1D C1 51 Q AO1 OEA 1D 43 C1 One of Eight Channels LOOPBACK 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5–43
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SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current range, VI: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V B port . . . . . . .
PAGE 379
SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS MIN TYP† MAX UNIT –1.2 V 2.85 VCC–1.1 3.4 V 0.33 0.5 VCC = 4.75 V, VCC = 4.75 V to 5.25 V, II = –18 mA IOH = –10 µA VCC = 4.75 V IOH = –3 mA IOH = –32 mA VCC = 4.75 V IOL = 20 mA IOL = 55 mA B port VCC = 4.
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SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2) VCC = 5 V, TA = 25°C MIN MIN MAX UNIT 150 MHz MAX fclock tw Clock frequency Pulse duration CLKAB/LEAB or CLKBA/LEBA 3.3 3.3 ns tsu th Setup time Data before CLKAB/LEAB or CLKBA/LEBA↑ 2.7 2.7 ns Hold time Data after CLKAB/LEAB or CLKBA/LEBA↑ 0.7 0.
PAGE 381
SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tr tf tr tf B-port input pulse rejection FROM (INPUT) VCC = 5 V, TA = 25°C TO (OUTPUT) MIN TYP MIN 150 AI (
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SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION 2.1 V 40 nH 9Ω From Output Under Test 30 pF Figure 1.
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SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION 2.1 V 9Ω 7V 500 Ω From Output Under Test CL = 50 pF (see Note A) S1 Open Test Point From Output Under Test CL = 30 pF (see Note A) 500 Ω LOAD CIRCUIT FOR A OUTPUTS S1 Open 7V Open LOAD CIRCUIT FOR B OUTPUTS 3V Timing Input TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH tw 1.5 V 3V 0V Input tsu 1.5 V 0V th VOLTAGE WAVEFORMS PULSE DURATION 3V Data Input 1.5 V 1.
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SN74FB2033K 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 D Compatible With IEEE Std 1194.
PAGE 385
SN74FB2033K 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 description (continued) Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the LOOPBACK input. When LOOPBACK is low, B-port data is the B-to-A input. When LOOPBACK is high, the output of the selected A-to-B logic element (before inversion) is the B-to-A input. The AO port-enable/-disable control is provided by OEA. When OEA is low or when VCC is less than 2.
PAGE 386
SN74FB2033K 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 Function Tables FUNCTION INPUTS OEA OEB OEB OMODE1 OMODE0 IMODE1 IMODE0 LOOPBACK FUNCTION/MODE L L X X X X X X L X H X X X X X X H L L L X X X AI to B, buffer mode X H L L H X X X AI to B, flip-flop mode X H L H X X X X AI to B, latch mode H L X X X L L L H X H X X L L L H L X X X L H L H X H X X L H L H L X X X H X L H X
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SN74FB2033K 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 Function Tables (Continued) LOOPBACK LOOPBACK Q† L B port H Point P‡ † Q is the input to the B-to-A logic element. ‡ P is the output of the A-to-B logic element (see functional block diagram).
PAGE 388
SN74FB2033K 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 functional block diagram 23 OEB OEB OMODE1 24 21 20 OMODE0 47 CLKAB/ LEAB Transceiver 1D C1 40 AI1 B1 50 P 1D C1 IMODE1 46 45 IMODE0 19 CLKBA/ LEBA 1D C1 51 Q AO1 OEA 1D 43 C1 One of Eight Channels LOOPBACK 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5–55
PAGE 389
SN74FB2033K 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any B output in the disabled or power-off state, VO . . . . . . . . . . . . . . –0.5 V to 3.
PAGE 390
SN74FB2033K 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 electrical characteristics over recommended operating free-air temperature range PARAMETER VIK VOH B port Except B port AO port TEST CONDITIONS VCC = 4.75 V, VCC = 4.75 V, II = –18 mA II = –40 mA VCC = 4.75 V to 5.25 V, IOH = –10 µA IOH = –3 mA VCC = 4.75 V AO port IOH = –32 mA IOL = 20 mA VCC = 4.75 V IOL = 55 mA IOL = 100 mA VOL B port VCC = 4.
PAGE 391
SN74FB2033K 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2) VCC = 5 V, TA = 25°C MIN MAX 0 150 MIN MAX UNIT 0 150 MHz fclock tw Clock frequency Pulse duration, CLKAB/LEAB or CLKBA/LEBA 3.3 3.3 ns tsu th Setup time, data before CLKAB/LEAB or CLKBA/LEBA↑ 2.7 2.7 ns Hold time, data after CLKAB/LEAB or CLKBA/LEBA↑ 0.7 0.
PAGE 392
SN74FB2033K 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2) FROM (INPUT) PARAMETER fmax tPLH TO (OUTPUT) VCC = 5 V, TA = 25°C MIN TYP MIN 150 tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH AI (through mode) B B (through mode) AO AI (transp
PAGE 393
SN74FB2033K 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION 2.1 V From Output Under Test 40 nH 9Ω 30 pF Figure 1.
PAGE 394
SN74FB2033K 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION 2.1 V 9Ω 7V 500 Ω From Output Under Test CL = 50 pF (see Note A) S1 Open Test Point From Output Under Test CL = 30 pF (see Note A) 500 Ω LOAD CIRCUIT FOR A OUTPUTS S1 Open 7V Open LOAD CIRCUIT FOR B OUTPUTS 3V Timing Input TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH tw 1.5 V 3V 0V Input tsu 1.5 V 0V th VOLTAGE WAVEFORMS PULSE DURATION 3V Data Input 1.5 V 1.5 V 1.
PAGE 395
SN74FB2040 8-BIT TTL/BTL TRANSCEIVER SCBS173M – NOVEMBER 1991 – REVISED JUNE 2001 D Compatible With IEEE Std 1194.
PAGE 396
SN74FB2040 8-BIT TTL/BTL TRANSCEIVER SCBS173M – NOVEMBER 1991 – REVISED JUNE 2001 ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING 0°C to 70°C QFP – RC Tube SN74FB2040RC FB2040 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
PAGE 397
SN74FB2040 8-BIT TTL/BTL TRANSCEIVER SCBS173M – NOVEMBER 1991 – REVISED JUNE 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V B port . . . . . . . . . . . .
PAGE 398
SN74FB2040 8-BIT TTL/BTL TRANSCEIVER SCBS173M – NOVEMBER 1991 – REVISED JUNE 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP† MAX UNIT VCC = 4.5 V, VCC = 4.5 V, II = –18 mA II = –40 mA VCC = 4.5 V, VCC = 4.5 V, IOH = –3 mA IOL = 24 mA 2.5 AO port VCC = 4.5 V IOL = 80 mA IOL = 100 mA 0.75 B port II Except B port VCC = 5.5 V, IIH‡ Except B port Except B port VCC = 5.5 V, VCC = 5.5 V, B port VCC = 5.
PAGE 399
SN74FB2040 8-BIT TTL/BTL TRANSCEIVER SCBS173M – NOVEMBER 1991 – REVISED JUNE 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL AI B tPLH tPHL B AO tPLH tPHL OEB B tPLH tPHL OEB B tPZH tPZL OEA AO tPHZ tPLZ OEA AO PARAMETER VCC = 5 V, TA = 25°C MIN MAX 6 2.4 6.5 4.2 5.6 2.7 5.8 2.3 3.8 5.7 1.9 6.2 2.3 4.2 5.9 2 8.2 3.7 5.1 6.
PAGE 400
SN74FB2040 8-BIT TTL/BTL TRANSCEIVER SCBS173M – NOVEMBER 1991 – REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION 2.1 V 16.5 Ω 7V S1 500 Ω From Output Under Test CL = 50 pF (see Note A) Open CL = 30 pF (see Note A) 500 Ω LOAD CIRCUIT FOR A OUTPUTS Input 1.5 V Test Point From Output Under Test LOAD CIRCUIT FOR B OUTPUTS 3V TEST S1 0V tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 1.5 V tPHL tPLH 1.55 V 1.55 V VOH Output VOL 3V Output Control tPZL 2V 1.55 V 1.55 V 1V tPHL 1.
PAGE 401
SN74FB2041A 7-BIT TTL/BTL TRANSCEIVER SCBS172L – NOVEMBER 1991 – REVISED JUNE 2001 D Compatible With IEEE Std 1194.
PAGE 402
SN74FB2041A 7-BIT TTL/BTL TRANSCEIVER SCBS172L – NOVEMBER 1991 – REVISED JUNE 2001 description (continued) Pins are allocated for the four-wire IEEE Std 1149.1 (JTAG) test bus, although currently there are no plans to release a JTAG-featured version. TMS and TCK are not connected and TDI is shorted to TDO. BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected.
PAGE 403
SN74FB2041A 7-BIT TTL/BTL TRANSCEIVER SCBS172L – NOVEMBER 1991 – REVISED JUNE 2001 functional block diagram OEB 1OEB 1OEA 1AI1 1AO1 2OEB 2OEA 2AI1 2AO1 46 45 47 40 51 50 25 20 38 2 2B1 52 36 3 2AI2 2AO2 2B2 4 34 8 2B3 2AI3 2AO3 1B1 6 26 3OEB 24 3OEA 3AI1 3AO1 3AI2 3AO2 3AI3 32 9 3B1 10 30 14 3B2 12 28 18 3B3 16 3AO3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5–71
PAGE 404
SN74FB2041A 7-BIT TTL/BTL TRANSCEIVER SCBS172L – NOVEMBER 1991 – REVISED JUNE 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V B port . . . . . . . . . . . .
PAGE 405
SN74FB2041A 7-BIT TTL/BTL TRANSCEIVER SCBS172L – NOVEMBER 1991 – REVISED JUNE 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP† MAX II = –18 mA II = –40 mA VCC = 4.5 V, VCC = 4.5 V, IOH = –3 mA IOL = 24 mA 2.5 AO port VCC = 4.5 V IOL = 80 mA IOL = 100 mA 0.75 B port II Except B port VCC = 5.5 V, VI = 5.5 V 50 µA IIH‡ Except B port VI = 2.7 V VI = 0.5 V 50 µA Except B port VCC = 5.5 V, VCC = 5.
PAGE 406
SN74FB2041A 7-BIT TTL/BTL TRANSCEIVER SCBS172L – NOVEMBER 1991 – REVISED JUNE 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL AI B tPLH tPHL B AO tPLH tPHL OEB B tPLH tPHL OEB B tPZH tPZL OEA AO tPHZ tPLZ OEA AO PARAMETER tsk(p)† tsk(o)† tt MIN MAX 5.1 2 5.6 4.1 5 2.5 5.3 MIN TYP MAX 2.3 3.9 2.6 2 3.6 4.8 1.7 5.3 2.3 3.8 4.9 2 6.
PAGE 407
SN74FB2041A 7-BIT TTL/BTL TRANSCEIVER SCBS172L – NOVEMBER 1991 – REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION 2.1 V 16.5 Ω 7V S1 500 Ω From Output Under Test CL = 50 pF (see Note A) Open CL = 30 pF (see Note A) 500 Ω LOAD CIRCUIT FOR A OUTPUTS Input 1.5 V Test Point From Output Under Test LOAD CIRCUIT FOR B OUTPUTS 3V TEST S1 0V tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 1.5 V tPHL tPLH 1.55 V 1.55 V VOH Output VOL 3V Output Control tPZL 2V 1.55 V 1.55 V 1V tPHL 1.
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General Information GTL GTLP ETL BTL/FB+ VME Application Reports Mechanical Data 6–1
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Contents SN74VMEH22501 VME 6–2 Page LVTTL-to-ETL 8-Bit Universal Bus Transceiver and Two 1-Bit Bus Transceivers With Split LVTTL Port, Feedback Path, and 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 410
SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 D Member of the Texas Instruments D D D D D D D D D D D D D 1OEBY 1A 1Y GND 2A 2Y VCC 2OEBY 3A1 GND LE 3A2 3A3 OE GND 3A4 CLKBA VCC 3A5 3A6 GND 3A7 3A8 DIR 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 description (continued) The B port operates at ETL levels, while the 1A and 2A inputs, 1Y and 2Y outputs, 3A port, and control inputs operate at LVTTL logic levels. All are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs.
PAGE 412
SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 functional description The SN74VMEH22501 is a high-drive (±48 mA), 8-bit UBT transceiver containing D-type latches and D-type flip-flops for data-path operation in transparent, latched, or flip-flop modes. Data transmission is true.
PAGE 413
SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 functional description for 8-bit UBT transceiver The 3A and 3B data flow in each direction is controlled by the OE and direction-control (DIR) inputs. When OE is low, all 3A- or 3B-port outputs are active. When OE is high, all 3A- or 3B-port outputs are in the high-impedance state.
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 logic diagram (positive logic) 48 1OEAB 1 1OEBY 2 46 1A 1B 3 1Y 2OEAB 2OEBY 41 8 43 5 2Y OE DIR CLKAB LE 2B PRODUCT PREVIEW 2A 6 14 24 32 11 17 CLKBA 9 3A1 1D C1 CLK 40 3B1 1D C1 CLK To Seven Other Channels Pin numbers shown are for the DGG and DGV packages.
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† PRODUCT PREVIEW Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . .
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 electrical characteristics over recommended operating free-air temperature range for A and B ports (unless otherwise noted) VIK VOH VOL UNIT –1.2 V VCC = 3.15 V to 3.45 V, IOH = –100 µA VCC–0.2 3A port and Y outputs VCC = 3.15 V IOH = –6 mA IOH = –12 mA 2.4 Any B port VCC = 3.
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 electrical characteristics over recommended operating free-air temperature range for A and B ports (unless otherwise noted) (continued) PARAMETER ICC MIN VCC = 3.45 V, IO = 0, VI = VCC or GND ICCD VCC = 3.
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 timing requirements over recommended operating conditions for UBT transceiver (unless otherwise noted) (see Figures 1 and 2) MIN fclock Clock frequency tw Pulse duration MAX UNIT MHz LE high 3A before LE↓ ↓ Setup time 3B before CLK↑ ↑ ↓ 3B before LE↓ 3A after CLK↑ ↑ 3A after LE↓ ↓ th Hold time 3B after CLK↑
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 switching characteristics over recommended operating conditions for UBT transceiver (unless otherwise noted) (see Figures 1 and 2) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ PRODUCT PREVIEW tPLZ FROM (INPUT) TO (OUTPUT) MIN TYP MAX UNIT MHz 3A 3B ns LE 3B ns CLKAB 3B ns OE 3B ns
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 skew characteristics for UBT for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air temperature (see Figures 1 and 2) PARAMETER tsk(LH) FROM (INPUT) TO (OUTPUT) 3A 3B ns CLKAB 3B ns 3B 3A ns CLKBA 3A ns MIN TYP† MAX UNIT tsk(HL) tsk(LH) t
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION A PORT 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH B-to-A Skew Open 6V GND Open LOAD CIRCUIT tw 3V 3V Timing Input 1.
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION B PORT 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH A-to-B Skew Open 6V GND Open LOAD CIRCUIT tw 3V 3V Timing Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 3V 1.5 V 0V tPZL 1.
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics tables show the switching characteristics of the device into the lumped load shown in the parameter measurement information (PMI) (see Figures 1 and 2). All logic devices are currently tested into this type of load.
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 driver in slot 11, with receiver cards in all other slots (full load) (continued) switching characteristics over recommended operating conditions for UBT (unless otherwise noted) (see Figure 3) FROM (INPUT) TO (OUTPUT) tPLH tPHL 3A 3B tPLH tPHL LE 3B tPLH tPHL CLKAB 3B tr‡ tf‡ Transition time, B port (10
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 driver in slot 1, with one receiver in slot 21 (minimum load) switching characteristics over recommended operating conditions for the bus transceiver function (unless otherwise noted) (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL 1A or 2A 1B or 2B tr‡ tf‡ Transition time, B port (10%–90%) Trans
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 driver in slot 1, with one receiver in slot 21 (minimum load) (continued) skew characteristics for UBT for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air temperature (see Figure 3) tsk(LH) FROM (INPUT) TO (OUTPUT) 3A 3B MIN TYP† 2 CLKAB 2.
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 driver in slot 1, with one receiver in slot 21 (minimum load) (continued) In general, the rise- and fall-time distribution is shown in Figure 5.
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SWITCHING FREQUENCY 200 180 I CC – Supply Current – mA 160 VCC = 3.45 V 140 120 VCC = 3.15 V 100 80 VCC = 3.
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 TYPICAL CHARACTERISTICS HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE t PHL – High-to-Low Propagation Delay Time – ns t PLH – Low-to-High Propagation Delay Time – ns 3.0 3.0 2.9 2.8 VCC = 3.15 V 2.7 2.6 VCC = 3.45 V 2.5 2.4 VCC = 3.3 V 2.3 2.2 2.1 2 –50 –30 –10 10 30 50 70 90 2.9 2.8 2.
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 VMEbus SUMMARY In 1989, multiplexing block transfer (MBLT) effectively increased the number of bits from 32 to 64, thereby doubling the transfer rate. In 1995, the number of handshake edges was reduced from four to two in the double-edge transfer (2eVME) protocol, doubling the data rate again.
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 protocol The basic single-cycle VMEbus data-transfer protocol is straightforward. The master puts addresses on the bus, delays a minimum of 35 ns, then asserts address strobe (AS*).
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 APPLICATION INFORMATION The SN74VMEH3222501KR is a two-die solution of the SN74VMEH22501 in the 96-ball LFBGA package (GKER). More information on the LFBGA package can be found at www.ti.com/sc/lfbga.
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 VITA 2.1 SIMULATION PROPOSAL FOR THE SN74VMEH22501 introduction This document is intended to form the basis of a statement of work for performance of simulation studies on standard VME64x backplanes using VITA 1.5 (draft, 2eSST) protocol. scope The scope of this VITA 2.
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SN74VMEH22501 LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS SCES357A – JULY 2001 – REVISED SEPTEMBER 2001 simulation matrix The simulation matrix of the adjustable-transceiver study shows the range of simulations to be carried out. Each case might have a number of different simulation runs, for example, multiple rise times in search of the boundary condition.
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General Information GTL GTLP ETL BTL/FB+ VME Application Reports Mechanical Data 7–1
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Contents Application Reports Fast GTLP Backplanes With the GTLPH1655 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Performance Backplane Design With GTL+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase the Speed of Parallel Backplanes 3× With GTLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Texas Instruments GTLP Frequently Asked Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Application Report SCBA015A - March 2001 Fast GTLP Backplanes With the GTLPH1655 Peter Forstner and Johannes Huchzermeier Standard Linear & Logic ABSTRACT This revision of the Fast GTL Backplanes With the GTL1655 application report addresses improvements, such as the improved OEC circuitry and implementation of the Texas Instruments TI-OPC circuitry, that have been incorporated in the GTLPH1655 device. These improvements significantly improve signal integrity in distributed loads.
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SCBA015A Features of the SN74GTLPH1655 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description: SN74GTLPH1655 – UBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SN74GTLPH1655: Link Between a GTLP Backplane and an LVTTL Module . . . . . . . . . . . . . . Termination Voltage, VTT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SCBA015A 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 LVTTL Input and Output Signal of SN74GTLPH1655, ERC = VCC, Unloaded, 10 MHz . . . . . GTLP Bus Signal, Slow Rise and Fall Times, ERC = VCC, Unloaded, 10 MHz . . . . . . . . . . . . LVTTL Input and Output Signal of SN74GTLPH1655, ERC = GND, Unloaded, 10 MHz . . . . . GTLP Bus Signal, Fast Rise and Fall Times, ERC = GND, Unloaded, 10 MHz . . . . . . . . . . . .
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SCBA015A Introduction Since the 1970s, bus systems have been used in every microprocessor system. In the early systems, the delay time of the driver was in the range of 15 ns to 20 ns, and the frequency of the system clock was about 1 MHz. The speed of the total system was determined primarily by the delay time of the active electronics, for example, the processor, gates, and bus drivers. With increasing clock rates, the bus began to limit the performance of the total system.
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SCBA015A Physical Principles In data sheets, the delay times of driver circuits are commonly given with a load circuit of 50 pF and 500 Ω at the outputs. However, this load circuit does not correspond well to the actual effective loads in current application. Rather, it is intended to match the conditions existing with IC testers. In particular, a load of this kind does not correspond to reality with bus systems.
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SCBA015A d = 2 cm LO ≈ 6 nH/cm CO ≈ 0.6 pF/cm CL ≈ 20 pF/2cm Ctot = CO + CL ≈ 10.6 pF/cm LO LO CO LO CL CO CL CO CL ZO = 25 Ω τ = 25 ns/m Figure 2. Physical Relationships on a Bus Line Table 1.
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SCBA015A 500 mV l=0m (∼10 pF) SN74LS00 5 ns l=1m (∼56 pF) 1V l = 11 m (∼616 pF) CL = 10 pF CL = 56 pF 10 ns CL = 616 pF SN74LS00 l 100 Ω ZO = 100 Ω CL Figure 3. Waveform on a Line Compared to Waveform With a Load Capacitor Transmission-Line Theory in Practice With lines of more than a certain length, the behavior of signals must be analyzed using transmission-line theory.
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SCBA015A ZO + ǸCȀLȀ t + ǸLȀ (1) (2) CȀ Where: ZO = impedance of the line (Ω) τ = propagation delay of the line (ns/m) L′ = inductive component of the line (nH/cm) C′ = capacitive component of the line (pF/cm) Table 2. Typical Characteristic Properties of Lines τ (ns/m) L′ (nH/cm) C′ (pF/cm) ZO (Ω) Point-to-point line between two components 5 to 10 0.5 to 1.
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SCBA015A This voltage edge now runs from the beginning of the line to the end. This first wave is called the incident wave. When the voltage wave reaches the end of the line, a reflected voltage wave is generated, the amplitude of which can be calculated from the reflection factor ρ, as shown in Equations 4 and 5.
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SCBA015A A B V A B ZO RTT = 0 W a) Short Circuit at End of Line 0 A V B τ A ZO B RTT = ZO b) Termination With RTT = ZO 0 A V B τ A B ZO RTT = ∞ 0 c) No Termination at End of Line Figure 5.
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SCBA015A Effects on Bus Lines Beginning of the Line: The Incident Wave A fundamental characteristic of bus drivers is their output resistance. Together with the line impedance, this forms a voltage divider (Equation 3) and, thus, is responsible for the amplitude of the incident voltage wave.
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SCBA015A This demonstrates one of the basic problems of bus systems. Since the amplitude of the incident wave depends on the voltage divider between the output resistance of the driver and the impedance of the line (≈25 Ω), a driver is needed with a particularly low output impedance. Only then is it possible to switch over a bus line with the incident wave. This is made more difficult because there are only two bus drivers at the beginning or end of the line.
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SCBA015A End of the Line: The Reflected Wave As explained in Transmission-Line Theory in Practice, a voltage wave is reflected at the end of a line, and this reflected wave moves back to the beginning of the line. The amplitude of the reflected wave is determined by the amplitude of the incident wave and the reflection factor (Equation 5). This reflection factor is determined by the line impedance and the termination resistance (Equation 4).
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SCBA015A V A A B B ZO = 25 Ω RTT = ∞ 0 a) No Termination A V B τ 2τ 3τ τ 4τ 5τ 6τ 7τ 3τ τ 4τ 5τ 6τ 7τ 5τ 6τ 7τ 5τ 6τ 7τ 5τ 6τ 7τ 5τ 6τ 7τ A ZO = 25 Ω B RTT = 25 Ω b) Termination With RTT = ZO 0 A V B τ 2τ A B ZO = 25 Ω RTT = 100 Ω c) Termination With ∞ > RTT > ZO 0 A B V τ 2τ 3τ τ 4τ B A ZO = 25 Ω d) AC Termination RTT = 100 Ω RTT × CT > 4τ CT VCC A ZO = 25 Ω B 0 V τ 2τ 3τ τ A 4τ B RTT1 = 180 Ω RTT2 = 220 Ω 0 RTT = RTT1 || RTT2 τ 2τ 3τ
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SCBA015A New Bus Systems Are Needed The cause of most problems with bus lines is the distributed capacitive loading on the line by the modules connected to it. The impact on TTL and CMOS buses is: • Very low signal speed on the line (about 25 ns/m, instead of 5 ns/m) • The impedance of the line is reduced from about 80 Ω to about 25 Ω. • As a result of the low impedance, adequate incident-wave amplitude is possible only with extremely low-resistance drivers.
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SCBA015A BTL Bus The specification of the BTL bus was conceived especially for large backplane systems. The basic circuit layout of a BTL bus is shown in Figure 9. +2.1 V Receiver RTT = ZO Driver ZO VREF = 1.55 V BTL Bus Figure 9. Circuit Concept of BTL Bus The outputs of a BTL driver are provided with open-collector pins. The maximum capacitance of an I/O pin was fixed at 5 pF. To attain this goal, a diode is connected in series with the output transistor.
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SCBA015A GTL Bus As shown in Figure 10, the basic circuit layout of the GTL bus is very similar to that of BTL. In this case, there also is a system with open-drain drivers and correct bus termination. The voltage levels of the logic states are 0.4 V in the low-logic state, and 1.2 V in the high-logic state. The signal amplitude is reduced to 0.8 V, whereby the threshold voltage lies exactly between the low and high levels, also at 0.8 V. +1.2 V Driver Receiver RTT = ZO ZO VREF = 0.
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SCBA015A Comparison Between BTL and GTL The structure of the two bus concepts (BTL and GTL) is similar. Both operate with open-collector/open-drain outputs and correct line termination. The most obvious difference is the definition of the logic voltage levels (Figure 11). The characteristics are listed and compared in Table 4. For large backplane wiring systems, the BTL circuits have the better characteristics, whereas the GTL bus features significantly lower power consumption.
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SCBA015A New Backplane Solution: SN74GTLPH1655 From TI It would be ideal to have a bus concept that combines all the desirable characteristics of both BTL and GTL. Meanwhile, TI offers a new generation of GTLP drivers that is compatible with existing GTL systems, but provides both the advantages of BTL and also the positive aspects of GTL drivers. A comparison is given in Table 5. • The logic levels are compatible with GTL buses, and also bus systems with GTLP levels.
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SCBA015A Features of the SN74GTLPH1655 Functional Description: SN74GTLPH1655 – UBT The SN74GTLPH1655 is described as a UBT, i.e., a bus driver for a wide variety of applications. The function of this component can be controlled and changed in accordance with the signals and static voltage levels applied to the various control inputs.
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SCBA015A SN74GTLPH1655: Link Between a GTLP Backplane and an LVTTL Module The SN74GTLPH1655 converts LVTTL-level signals (A port) into GTL- or GTLP-level signals (B port), and vice versa. The user decides, by choosing the termination voltage and the reference voltage, which level will be provided on the B-port side (see Table 6). The A port is, in every case, compatible with LVTTL.
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SCBA015A Termination Voltage, VTT There are various rules and techniques regarding proper line termination that should be observed for a successful development using SN74GTLPH1655. The termination voltage (VTT) should be derived from a voltage regulator. The current requirements, e.g., up to 100 mA per output, must be observed. There are various voltage regulators available that meet these requirements.
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SCBA015A Since the bypass capacitor should have the lowest possible inductance, it is recommended that ceramic capacitors in surface-mount packages be used. The value of capacitance can be calculated from Equation 6. C I Dt DU (6) I = 50 mA For bidirectional lines with a termination resistor at both ends of each line, a maximum of one-half the output current of an SN74GTLPH1655 (IO = 100 mA) can flow through one of the two termination resistors.
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SCBA015A Static Characteristics of the SN74GTLPH1655 An understanding of the static characteristics of a component is necessary for a circuit development to be successful. The input and output characteristics of the SN74GTLPH1655 were, therefore, measured under laboratory conditions. Input Characteristics In principle, the input characteristics appear identical on both sides (A and B ports) of the device.
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SCBA015A Bus-Hold Circuit If the input characteristics of the LVTTL side (A port) are recorded in small increments, and over a narrow range of current, the curve shown in Figure 17 results. This curve clearly demonstrates the effectiveness of the bus-hold circuit. To change the logic state stored by the bus-hold circuit, a current of about 250 µA must be overridden. This circuit is useful when, for example, all drivers on the bus are in a high-impedance state. Thus, an undefined state can be prevented.
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SCBA015A GTLP Output Characteristics Because the SN74GTLPH1655 has been conceived as an interface between LVTTL partial systems and a GTLP backplane, the output characteristics of both sides are shown here. The characteristics for the various logic states of the output stage are shown in a single voltage-current diagram. The principle of the GTLP bus is based on open-drain drivers, as shown in Figure 18. To Other Inputs Output VTT VTT RTT Input RTT GTLP Bus Figure 18.
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SCBA015A SN74GTLPH1655 Output Characteristics, Static High, Low, and Off State 8 7 6 Voltage – V 5 VOFF @ VREF = 0 . . . 1.5 V VOH @ VREF = 1.5 V 4 VOH @ VREF = 1.0 V 3 2 VOH @ VREF = 0.5 V VOH @ VREF = 0 V VOL @ VREF = 0 . . . 1.5 V VOH @ VREF = 0 . . . 1.5 V 1 0 –1 –100 –80 –60 –40 –20 0 Current – mA 20 40 60 80 100 Figure 19. Output Characteristics of GTLP Port of SN74GTLPH1655 In the high state, the output transistor is blocking up to VREF + one diode forward voltage.
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SCBA015A LVTTL Output Characteristics The output characteristics of the LVTTL output side of the SN74GTLPH1655 are shown in Figure 20, recorded with a supply voltage VCC = 3.3 V. The output resistance for the low state is around 10 Ω, and in the case of the high state, a value of about 25 Ω is typical. 5V 4V Input Voltage 3V High 2V Low 1V 0V –1 V –100 mA –80 mA –60 mA –40 mA –20 mA 0 mA 20 mA 40 mA 60 mA 80 mA 100 mA Input Current Figure 20.
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SCBA015A TI-OPC Circuitry TI-OPC circuitry is a new feature of the GTLP backplane family. This circuit improves signal integrity by using a control circuit that compares the output voltage at the GTLP port with the reference voltage. The principle is shown in Figure 21. VTT VREF TI-OPC RTT Figure 21.
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SCBA015A ERC = VCC, GND VCC VTT RTT = 25 Ω Probe Signal Generator With Different Edge Rates Figure 22. Setup for Measuring Edge Rate at GTLP Side of SN74GTLPH1655 Additional measurement results on the SN74GTLPH1655 test board are presented in a later section, which explains the behavior with a bus under realistic conditions. The measurement results for falling edges are shown in Figures 23 and 24; Figures 25 and 26 show the curves for rising edges.
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SCBA015A 4.00 V 3.00 V Input 2.00 V Output 1.00 V 0.00 V –1.00 V ERC = GND –2.00 V 5 ns 10 ns 15 ns 20 ns 25 ns 30 ns 35 ns Figure 24. Falling Edge, ERC = GND (Fast Edges), Input Signals tf = 2 ns, 10 ns 4.00 V 3.00 V Input Output 2.00 V 1.00 V 0.00 V –1.00 V ERC = VCC –2.00 V 0 ns 5 ns 10 ns 15 ns 20 ns 25 ns 30 ns Figure 25.
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SCBA015A 4.00 V 3.00 V Input Output 2.00 V 1.00 V 0.00 V –1.00 V ERC = GND –2.00 V 0 ns 5 ns 10 ns 15 ns 20 ns 25 ns 30 ns Figure 26. Rising Edge, ERC = GND (Fast Edges), Input Signals tr = 2 ns, 10 ns Removal and Insertion Under Voltage and Partially Switched-Off Systems If it is possible to remove and reinsert plug-in boards in a system while it remains in operation (live insertion), special precautions must be taken with the signal lines.
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SCBA015A High Data on Bus Volts Max Peak With Precharge Low Data on Bus Max Peak With Precharge Possible Peak Without Precharge Precharge Level = VTH VTH Time Possible Peak Without Precharge Point of Live Insertion During High on Bus Point of Live Insertion During Low on Bus Figure 27. Influence of Precharge Function on Bus Signal The SN74GTLPH1655 has the characteristics discussed above, which are necessary for the successful development of a live-insertion application.
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SCBA015A Measurements on GTLPH1655 Test Board A GTLPH1655 test board has been constructed to examine the characteristics of the SN74GTLPH1655 in a practical application. The principle of this board is shown in Figure 28. I = 40 cm I = 20 cm Backplane Bus, ZO = 25 Ω, τ = 16.25 ns/m SN74GTLPH1655 Midpoint SN74GTLPH1655 Figure 28. Principle of Construction of GTLP Bus on GTLPH1655 Test Board This bus consists of a straight connecting line, 40 cm long, between two SN74GTLPH1655 devices.
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SCBA015A The measurement results presented in Figures 29 through 52 show: • The LVTTL input signal of the SN74GTLPH1655 that drives the bus line, together with the LVTTL output signal of the SN74GTLPH1655 receiver that is situated at the end of the GTLP bus. For this, the load of the receiver was varied. The diagrams show the curves for RL = ∞ (unloaded output) and for RL = 50 Ω. • Waveforms on the GTLP bus line: – GTLP output signal of the SN74GTLPH1655 that drives the bus line, i.e.
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SCBA015A Measurement Results With an Unloaded Backplane (ZO = 30 Ω, RTT = 25 Ω) Input/Output Signal at f = 10 MHz 3.50 V Signal at Output of Receiver, Without RL 2.50 V Signal at Output of Receiver, RL = 50 Ω 1.50 V Signal at Input of Transmitter 0.50 V –0.50 V 0 ns 20 ns 40 ns 60 ns 80 ns 100 ns Figure 29. LVTTL Input and Output Signal of SN74GTLPH1655, ERC = VCC, Unloaded, 10 MHz 2.00 V ERC = VCC Beginning of Line Middle of Line 1.50 V End of Line 1.00 V 0.50 V 0.
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SCBA015A Input/Output Signal at f = 10 MHz 3.50 V Signal at Output of Receiver, Without RL 2.50 V Signal at Output of Receiver, RL = 50 Ω 1.50 V Signal at Input of Transmitter 0.50 V –0.50 V 0 ns 20 ns 40 ns 60 ns 80 ns 100 ns Figure 31. LVTTL Input and Output Signal of SN74GTLPH1655, ERC = GND, Unloaded, 10 MHz 2.00 V ERC = GND Beginning of Line Middle of Line 1.50 V End of Line 1.00 V 0.50 V 0.00 V 0 ns 20 ns 40 ns 60 ns 80 ns 100 ns Figure 32.
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SCBA015A 4.00 V Signal at Input of Transmitter 3.00 V Signal at Output of Receiver, Without RL Signal at Output of Receiver, RL = 50 Ω 2.00 V 1.00 V 0.00 V Input/Output Signal at f = 50 MHz –1.00 V 0 ns 5 ns 10 ns 15 ns 20 ns 25 ns 30 ns 35 ns Figure 33. LVTTL Input and Output Signal of SN74GTLPH1655, ERC = VCC, Unloaded, 50 MHz 2.00 V ERC = VCC 1.50 V Beginning of Line Middle of Line 1.00 V End of Line 0.50 V 0.00 V 0 ns 5 ns 10 ns 15 ns 20 ns 25 ns 30 ns 35 ns Figure 34.
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SCBA015A 4.00 V Signal at Input of Transmitter 3.00 V Signal at Output of Receiver, Without RL 2.00 V Signal at Output of Receiver, RL = 50 Ω 1.00 V 0.00 V Input/Output Signal at f = 50 MHz –1.00 V 0 ns 5 ns 10 ns 15 ns 20 ns 25 ns 30 ns 35 ns Figure 35. LVTTL Input and Output Signal of SN74GTLPH1655, ERC = GND, Unloaded, 50 MHz 2.00 V ERC = GND 1.50 V Beginning of Line 1.00 V Middle of Line End of Line 0.50 V 0.00 V 0 ns 5 ns 10 ns 15 ns 20 ns 25 ns 30 ns 35 ns Figure 36.
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SCBA015A 4.00 V 3.50 V Input/Output Signal at f = 160 MHz 3.00 V Signal at Output of Receiver, Without RL 2.50 V 2.00 V Signal at Output of Receiver, RL = 50 Ω 1.50 V 1.00 V Signal at Input of Transmitter 0.50 V 0.00 V –0.50 V –1.00 V 0 ns 2 ns 4 ns 6 ns 8 ns 10 ns 12 ns 14 ns 16 ns 18 ns 20 ns Figure 37. LVTTL Input and Output Signal of SN74GTLPH1655, ERC = VCC, Unloaded, 160 MHz 3.00 V ERC = VCC Middle of Line 2.00 V End of Line Beginning of Line 1.00 V 0.00 V –1.
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SCBA015A 4.00 V 3.50 V Input/Output Signal at f = 160 MHz Signal at Output of Receiver, Without RL 3.00 V 2.50 V 2.00 V Signal at Input of Transmitter 1.50 V Signal at Output of Receiver, RL = 50 Ω 1.00 V 0.50 V 0.00 V –0.50 V –1.00 V 0 ns 2 ns 4 ns 6 ns 8 ns 10 ns 12 ns 14 ns 16 ns 18 ns 20 ns Figure 39. LVTTL Input and Output Signal of SN74GTLPH1655, ERC = GND, Unloaded, 160 MHz 3.00 V ERC = GND Middle of Line 2.00 V End of Line Beginning of Line 1.00 V 0.00 V –1.
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SCBA015A Measurement Results With a Loaded Backplane (ZO = 25 Ω, RTT = 25 Ω) 3.50 V Signal at Output of Receiver, Without RL Input/Output Signal at f = 10 MHz 2.50 V 1.50 V Signal at Output of Receiver, RL = 50 Ω 0.50 V Signal at Input of Transmitter –0.50 V 0 ns 20 ns 40 ns 60 ns 80 ns 100 ns Figure 41. LVTTL Input and Output Signal of SN74GTLPH1655, ERC = VCC, Loaded, 10 MHz 2.00 V ERC = VCC Beginning of Line 1.50 V Middle of Line 1.00 V 0.50 V End of Line 0.
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SCBA015A 3.50 V Input/Output Signal at f = 10 MHz Signal at Output of Receiver, Without RL 2.50 V Signal at Output of Receiver, RL = 50 Ω 1.50 V Signal at Input of Transmitter 0.50 V –0.50 V 0 ns 20 ns 40 ns 60 ns 80 ns 100 ns Figure 43. LVTTL Input and Output Signal of SN74GTLPH1655, ERC = GND, Loaded, 10 MHz 2.00 V ERC = GND 1.50 V Beginning of Line 1.00 V End of Line 0.50 V 0.00 V 0 ns Middle of Line 20 ns 40 ns 60 ns 80 ns 100 ns Figure 44.
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SCBA015A Input/Output Signal at f = 50 MHz 3.50 V Signal at Input of Transmitter 2.50 V Signal at Output of Receiver, Without RL 1.50 V Signal at Output of Receiver, RL = 50 Ω 0.50 V –0.50 V 0 ns 5 ns 10 ns 15 ns 20 ns 25 ns 30 ns 35 ns Figure 45. LVTTL Input and Output Signal of SN74GTLPH1655, ERC = VCC, Loaded, 50 MHz 2.00 V ERC = VCC 1.50 V Beginning of Line 1.00 V End of Line Middle of Line 0.50 V 0.00 V 0 ns 5 ns 10 ns 15 ns 20 ns 25 ns 30 ns 35 ns Figure 46.
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SCBA015A Input/Output Signal at f = 50 MHz 3.50 V Signal at Input of Transmitter 2.50 V Signal at Output of Receiver, Without RL 1.50 V ‘ Signal at Output of Receiver, RL = 50 Ω 0.50 V –0.50 V 0 ns 5 ns 10 ns 15 ns 20 ns 25 ns 30 ns 35 ns Figure 47. LVTTL Input and Output Signal of SN74GTLPH1655, ERC = GND, Loaded, 50 MHz 2.00 V ERC = GND Beginning of Line 1.00 V End of Line Middle of Line 0.00 V 0 ns 5 ns 10 ns 15 ns 20 ns 25 ns 30 ns 35 ns Figure 48.
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SCBA015A 4.00 V Input/Output Signal at f = 160 MHz 3.50 V Signal at Output of Receiver, Without RL 3.00 V 2.50 V Signal at Input of Transmitter Signal at Output of Receiver, RL = 50 Ω 2.00 V 1.50 V 1.00 V 0.50 V 0.00 V –0.50 V 0 ns 2 ns 4 ns 6 ns 8 ns 10 ns 12 ns 14 ns 16 ns 18 ns 20 ns Figure 49. LVTTL Input and Output Signal of SN74GTLPH1655, ERC = VCC, Loaded, 160 MHz 2.00 V ERC = VCC 1.50 V Beginning of Line Middle of Line End of Line 1.00 V 0.50 V 0.
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SCBA015A 4.00 V 3.50 V Input/Output Signal at f = 160 MHz Signal at Output of Receiver, Without RL 3.00 V 2.50 V 2.00 V 1.50 V Signal at Output of Receiver, RL = 50 Ω 1.00 V Signal at Input of Transmitter 0.50 V 0.00 V –0.50 V 0 ns 2 ns 4 ns 6 ns 8 ns 10 ns 12 ns 14 ns 16 ns 18 ns 20 ns Figure 51. LVTTL Input and Output Signal of SN74GTLPH1655, ERC = GND, Loaded, 160 MHz 2.00 V ERC = GND 1.50 V Beginning of Line Middle of Line End of Line 1.00 V 0.50 V 0.
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SCBA015A Summary The SN74GTLPH1655 from TI provides engineers who develop fast and complex bus systems with a high-performance bus driver that is particularly suitable for the design of modern low-voltage systems. Very high signal-propagation speeds are possible, as a result of the increased drive capability of 100 mA, compared with standard GTL circuits (40 mA), and the selectable edge rate. Bus lines with low line impedances of about 22 Ω can be used with the SN74GTLPH1655.
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SCBA015A References SN74GTLPH1655 16-Bit LVTTL-to-GTL+ Adjustable-Edge-Rate Universal Bus Transceiver, Data Sheet, October 1999, literature number SCES294. GTL, BTL, and ETL Logic – High-Performance Backplane Drivers, Data Book, 1997, literature number SCED004. Logic Selection Guide and Data Book, CD-ROM, April 1998, literature number SCBC001B. GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic, March 1997, literature number SCEA003A.
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SCBA015A Glossary BTL Backplane Transceiver Logic ERC Edge-Rate Control GND Ground potential GTL Gunning Transceiver Logic GTLP Gunning Transceiver Logic Plus I/O Input/Output Live insertion Removal and reinsertion of modules during operation LVTTL levels 3.
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High-Performance Backplane Design With GTL+ SCEA011A October 1999 7–53
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
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Contents Title Page Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–57 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–57 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Abstract Results from a system that demonstrates the performance of GTL+ devices in a backplane are provided. The Texas Instruments (TI) GTL16622A is the example used in the design of the physical backplane. The TI backplane demonstration system is a useful tool for designers in understanding issues related to loading effects, termination, signal integrity, and data-transfer rate in a high-performance backplane environment.
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1.2 V VOH 0.85 V 0.8 V 0.75 V VIH VREF VIL 0.4 V 1.5 V VOH 1.2 V VIH 1.0 V VREF 0.8 V VIL 0.6 V VOL 0 GND GTL+ VOL 0 GND GTL Figure 1. GTL/GTL+ Switching Levels GTL+ achieves high performance with the help of the low signal voltage swing.1 The typical swing for GTL+ is from 0.6-V low (VOL) to 1.5-V high (VOH) maximum. TI uses tighter threshold regions, VIH at 1.05 V, VIL at 0.95 V, and VOL at 0.55 V, to provide better signal integrity in its stand-alone devices.
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Medium- and high-performance backplanes can be modeled as a distributed load. This is because performance drives a multidrop architecture, where the capacitance is distributed over the length of the backplane. To design an optimized mediumor high-performance backplane, a few concepts must be understood.
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1.6 1.4 Voltage – V 1.2 1.0 0.8 0.6 0.4 0.2 0 10 20 30 40 50 60 70 80 Time – ns Figure 4. GTL16622A H-SPICE Simulation (Lumped Load, 33 MHz) 2.8 2.6 2.4 2.2 Voltage – V 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0 10 20 30 40 50 60 70 80 Time – ns Figure 5. GTL16622A H-SPICE Simulation of a Backplane (Distributed Load, 33 MHz) The added capacitance and inductance in the distributed load cause reflections that result in problems that include reduced noise margins.
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Table 1. Noise-Margin Comparison DEVICE TYPE NOISE MARGIN (mV) UPPER LOWER GTL 350 350 GTL+ 450 400 Another issue to consider in backplane design is crosstalk. Crosstalk, an effect of capacitive coupling in backplanes, can also result in false switching. Crosstalk between signal lines can be approximated as being inversely proportional to the distance between the signal lines and directly proportional to the distance between the signal lines and the ground plane.
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Crystal Oscillator Clock Driver for Each Set of Eight Cards 7 8 9 Card Card Card Card Card Card Card Card Termination Resistor Data Generation 10 11 12 13 14 15 16 Card 6 Card 5 Card 4 Card 3 Card 2 Card 1 Card C3 C2 Card C1 X1 1.5-V Regulator VTT Generation 3.3 V 5V AC Power Figure 6.
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Unloaded Line Impedance Inputs Outputs Line Zo = Line Co (pF) = 4.10 /in. Device Cio (pF) = 6.00 Load Spacing D1 (in) = Stub Length Lo (pH) = 10250.00 /in. tpd (ps) = 205.00 /in. 0.875 Ct (pF) = 10.96 D2 (in) = 1.0625 Cd (pF) = 12.53 Stub Co (pF) = 2.60 Connector CC (pF) = 0.70 Connector Pads CP (pF) = 1.00 Via Cvia (pF) = 0.50 50.00 /in. Effects of Cd on Impedance (Loaded) tpd (ps) = 412.85 /in. Zo (eff) = 24.8 RT Figure 8.
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Results Laboratory data were taken using the demonstration backplane and compared to HSPICE simulation results to validate the performance of the GTL16622A on the backplane. Figure 7 is the reference to give the position of driver and receiver cards in the backplane. Results for TI’s newest addition, the GTL16612A, demonstrate the throughput capability in a very high-performance backplane.
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The slot closest to the driver (slot 2) shows the worst-case ringing because it sees the fastest rise time of the IC driver compared to the slots that are farther away from the driver. The worst-case signal at slot 2 also is due to the effect of reflected energy that is maximum in the receiver closest to the driver.3 Correlation Figure 11 shows laboratory versus simulation results for the GTL16622A on the demonstration board. The results shown are for the receiver at slot 2 (closest to the driver card).
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Moving Forward With the GTL16612A TI has continued to improve the characteristics and features of the GTL family to provide higher throughput rates at backplane frequencies up to 80 MHz. These higher frequencies allow designers to transmit increased amounts of data on their board, achieving high bit rates in their systems. The newest device in the GTL family, the GTL16612A, an improved version of the GTL16612, is capable of operating at frequencies as high as 80 MHz.
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Figure 14 shows simulation results for the GTL16612A operating at high clock rates of 80 MHz and 100 MHz. The innovative design of the 18-bit device provides for extremely high throughput on a backplane if the timing requirements of the board can be met. 1.6 Receiver in Slot 2 1.4 Voltage – V 1.2 100 MHz 1.0 80 MHz 0.8 0.6 0.4 0.2 25 30 35 40 45 Time – ns Figure 14.
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Glossary Incident-wave switching Voltage transition that is strong enough to switch the input of the receiver on the first edge of the wave. This implies that subsequent reflections do not change the state of the receiver to its previous state. Noise margin Difference between the driver or receiver threshold voltage and the voltage on the bus. A noise margin comparison for the GTL/GTL+ technologies is shown in Table 1.
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T H E W O R L D L E A D E R I N L O G I C P R O D U C T S Increase the speed of parallel backplanes 3x with GTLP 7-69
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For high-speed parallel backplanes, GTLP is the answer. Migrate to next-generation speed In today's interconnected, bandwidthhungry world, designers can easily increase by two to three times the data throughput speed of their networking, communications and telecommunications systems by migrating to TI's new GTL-Plus (GTLP) logic family for parallel backplanes.
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Improving on a good thing In recent years, GTL logic has become increasingly popular in point-to-point applications and backplane systems with a limited number of slots. Now, GTLP brings the high-speed advantages of GTL to medium- and heavily loaded parallel backplanes. GTLP transceivers are differential input, open-drain n-channel devices.
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Live board insertion Many backplane systems are used in communication and networking applications where availability 24 hours a day, seven days a week (24/7) is a must. As a result, boards must be inserted or removed from the system while it is still running. TI has included three kinds of internal circuitry to accomplish faultproof live insertion. First, by including a blocking diode and removing a clamping diode, unexpected device behavior is eliminated when power is fully or partially removed.
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The Pluses of GTLP • Two to three times faster data throughput on heavily loaded parallel backplanes • Live insertion of cards into GTLP backplanes for high-availability systems • 3.
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G GTLP GTLP GTLP GTLP Packaging Options GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP 96-Ball BGA Area = 74mm2 HT. = 1.4mm LP = 0.8mm 114-Ball BGA GTLP 2 Area = 88mm HT. = 1.4mm LP = 0.8mm 48-Pin SSOP Area = 171mm2 HT. = 2.0mm LP = 0.65mm 48-Pin TSSOP Area = 105mm2 HT. = 1.2mm LP = 0.65mm GTLP GTLP GTLP 24-Pin SOIC Area = 160mm2 GTLP HT. = 2.65mm LP = 1.27mm GTLP GTLP GTLP GTLP GTLP 48-Pin TVSOP Area = 63mmG2 TLP HT. = 1.2mm LP = 0.
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Application Report SCEA019 - January 2001 Texas Instruments GTLP Frequently Asked Questions Steve Blozis Standard Linear & Logic ABSTRACT Using a question-and-answer format, advantages of TI’s GTLP devices, particularly for backplane applications, are presented, as well as differences between GTLP and GTL/LVDS devices.
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SCEA019 - January 2001 Table of Contents Introduction ............................................................................................................................ 7–78 What is a backplane?............................................................................................................. 7–78 What is a backplane protocol? ............................................................................................... 7–78 Should I use a parallel or serial architecture?..............
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SCEA019 - January 2001 38. How do I get IBIS Models?................................................................................................... 7–119 39. How do I get HSPICE Models? ............................................................................................ 7–120 40. Why does the unencrypted Level-37 HSPICE model require a confidentiality agreement? .. 7–120 41. How should I request a confidentiality agreement? ..............................................................
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SCEA019 - January 2001 Introduction This information on GTLP and backplane design is presented in the frequently asked-question (FAQ) format. The GTLP FAQs allow the novice backplane user to learn more about parallel backplanes and allows the experienced backplane user to better design-in and use the higher performance of GTLP devices. Any questions not adequately addressed or applications you want highlighted can be sent to GTLP@list.ti.com for action and possible future insertion into the FAQs.
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SCEA019 - January 2001 4 If I use a parallel single-ended backplane, why do I need to use backplane-optimized transceivers and not just typical LVT or FCT devices? The physics involved with a distributed-capacitance load limits the maximum frequency, unless the device is optimized with slower edge rates that ring less in these environments. FCT or LVT can offer only up to about 25 MHz, and, even then, signal integrity might be poor.
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SCEA019 - January 2001 6 What is GTL? GTL is a reduced-voltage-swing (<1 V), open-drain/collector, differential-input JEDEC standard that allows higher frequency operation than TTL devices in point-to-point and lightly loaded memory-interface-bus applications. The reduced voltage swing reduces EMI and allows higher frequencies. For best signal integrity, the open-drain/collector arrangement facilitates matching the termination resistor (RTT) to the trace impedance (ZO).
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SCEA019 - January 2001 GTL devices are bidirectional translators (see Figure 2). A-Port (daughter-card side) input can be 5-V CMOS, TTL, or LVTTL logic levels; output is LVTTL, which is compatible with TTL logic levels. B-Port (backplane side) input and output is GTL or GTL+ signal levels. 5V VCC 4.44 VOH 3.5 5V V VIH VCC 3.3 V 2.5 1.5 Vt VIL 2.4 VOH 2.4 VOH 2.0 VIH 2.0 VIH 1.5 Vt 1.5 Vt 1.5 V 1.2 V 0.5 0 VOL GND 5V CMOS Input 0.8 VIL 0.8 VIL 0.4 VOL 0.
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SCEA019 - January 2001 As shown in Figure 3, Vref is set by an R/2R resistor network between VTT and GND. The resistor network maintains balanced upper and lower noise margins for any terminationvoltage fluctuations. A 0.1- to 0.01-µF bypass capacitor buffers voltage fluctuations and should be as close to the Vref pin as possible. Vref Figure 3. GTL R/2R Resistor Network Vref is generated locally on each card, using size 805 1-kΩ and 2-kΩ ±1% resistors.
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SCEA019 - January 2001 7 What is the difference between GTLP and GTL? TI introduced the GTL family of devices in 1993. GTL devices were designed with faster edge rates to drive a lumped load. Originally, these devices were designed for small buses on a board, e.g., memory applications, and did not support hot insertion. The devices rang excessively when used in larger multipoint distributed-capacitance backplane applications because of the faster edge rate.
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SCEA019 - January 2001 All three devices shown in Figure 4 have bus hold on the LVTTL A port. But, only the newer TI GTLP family uses H in the part number to denote bus hold, because there are several devices in the GTLP family without bus hold. All TI GTL devices have bus hold, while the competitor’s GTL or GTLP family has some of both; the only way to determine the configuration is by referring to the data sheet.
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SCEA019 - January 2001 Incident-wave switching ensures that the first received signal during a transition (low to high or high to low) is valid, and reduces wait time. Reflected-wave switching requires additional wait time as shown in Figure 6.
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SCEA019 - January 2001 8 What is distributed capacitance? Figure 7 is a simplified backplane physical representation, where an equivalent capacitive load of 12 pF replaces the receivers. The transmitter also has an equivalent capacitive load of 12 pF. d=1 R TT R TT B Tx A 12 pF 12 pF 12 pF 12 pF 12 pF 12 pF 12 pF 12 pF 12 pF 12 pF 1 = 10" Figure 7.
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SCEA019 - January 2001 The capacitance in the chain illustrated in Figure 8 is summed as follows: Cvia = capacitance of via = 0.5 pF Cstub1 = capacitance of Stub1 = 0.0625 inch × 2.6 pF/inch = 0.16 pF Ccpad1 = capacitance of Cpad1 = 0.5 pF Ccon = capacitance of connector = 0.74 pF Ccpad2 = capacitance of Cpad2 = 0.5 pF Cstub2 = capacitance of Stub2 = 1 inch × 2.6 pF/inch = 2.
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SCEA019 - January 2001 This illustrates why the termination-resistor values should be lower than the typical 50-Ω natural transmission-line impedance in multipoint applications. Matching the termination resistor with the effective trace impedance ensures incident-wave switching and better signal integrity. Higher-drive (100 mA) devices are offered because termination values lower than 38 Ω often are required. For example, in a 20-slot, slot pitch = 0.
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SCEA019 - January 2001 The waveforms in Figure 9 show the effect on signal integrity in over-matched and undermatched termination conditions. RTT should be less than or equal to ZO(eff) for optimum signal integrity and upper noise margin. Over-Matched Termination (RTT < ZO(eff)) VOH Matched Termination (RTT = ZO(eff)) Under-Matched Termination (RTT > Z ) 1.5 V Noise Margin 1.0 V 0.5 V VOL GND Figure 9.
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SCEA019 - January 2001 10 How should I terminate GTL devices in short-distance applications? GTL products are open drain, so they must be connected to VTT via proper RTT termination resistors. One question is that if GTL or GTLP is used to transmit signals on a daughter card, the distance is very short, about 4 cm to 6 cm.
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SCEA019 - January 2001 G TLP T ra n s c ei v e r A S IC o r D S P R TT M ic ro s trip o r S trip lin e T ra c e C onn ector G TLP T ra n s c e iv e r Figure 10. Heavily Loaded, Distributed-Capacitance Backplane Installation GTLP devices allow higher frequencies on the backplane because of the improved signal-integrity/incident-wave switching the results from the reduced swing (<1 V), lower slew rate (0.35 V/ns to 0.5 V/ns), and matched termination resistors.
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SCEA019 - January 2001 Lumped loads normally are associated with point-to-point applications. However, GTLP devices have been designed into actual backplane netlists and a resistance/inductance/ capacitance (RLC) network that closely matches the results in a backplane. TI’s GTLP devices are tested into a lumped load, as are all other devices offered by TI and other semiconductor manufacturers.
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SCEA019 - January 2001 13 How does GTLP compare to other single-ended and differential bus solutions? Reduced voltage swing, lower slew rate, and open-drain construction allow GTLP devices to operate at higher frequencies than TTL devices in parallel-backplane architecture. GTLP offers an alternative to high-data-throughput differential devices where parallel backplanes are the best solution and higher data throughput is now required (see Table 2). B B 5 3.
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SCEA019 - January 2001 2500 Data Transfer Rate (Mbps) General Purpose Logic GTLP 655 400 CML 1394.a LVDS=RS-644 35 10 RS-422 RS-485 1 0.1 RS-232 RS-423 0.01 1 10 100 1000 Cable Length (meters) Figure 12. Data Transfer Rate (Mbps) More information on TI’s vast array of parallel and serial technologies can be found in the Comparing Bus Solutions application report, literature number SLLA067.
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SCEA019 - January 2001 14 What is the maximum data throughput using GTLP? Data throughput is a function of clock frequency times the bit width of the backplane. Increasing the maximum frequency or backplane bit width increases data throughput. GTLP devices can operate at speeds up to 175 MHz into a distributed load with good signal integrity. A 32-bit backplane operating at 110-MHz clock frequency has a data transfer rate of 1.
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SCEA019 - January 2001 Propagation delay is a function of the edge rate. Only high-drive GTLP devices are able to operate at both slow and fast edge rates, with a maximum tpd of about 7 ns and 5.5 ns, respectively. Medium-drive devices operate only at the slow edge rate, with a maximum tpd of about 7 ns. These are design goals, and actual values may be different. Setup and hold times and skew are inherent in the device.
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SCEA019 - January 2001 To improve backplane performance, review the High-Performance Backplane Design With GTL+ application report, literature number SCEA011A, and Basic Design Considerations for Backplanes application report, literature number SZZA016A. Additional information on calculating backplane impedance can be found at www.ultracad.com. There is detailed information on microstrip and stripline calculations and an impedance calculator that can be downloaded.
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SCEA019 - January 2001 16 What GTLP devices are available and how much will they cost? The first wave of TI’s GTLP devices comprises seven medium-drive and six high-drive devices. They are offered in ultra compact (LFBGA/VFBGA), small (TVSOP), medium (TSSOP), or large (SOIC or SSOP) packages.
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SCEA019 - January 2001 17 These function numbers are different. How do they compare to normal logic functions? When the GTL family was introduced, it was decided to differentiate GTL function numbers from other similar logic functions because of the Vref pin and the reduced B-port GTL signal levels. The first GTL device (SN74GTL16612) has exactly the same pinout as the 3.3-V VCC ‘16601 universal bus transceiver, except that the two VCC pins on the B-port side serve different purposes.
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SCEA019 - January 2001 GTLP device naming considerations are: • The 16XXX and 32XXX function numbers signify WidebusTM (16 to 18 bits) and Widebus+TM (32 to 36 bits) bit widths. Typically, octals are XXX only. • Function numbers of XX9XX signify single-VCC operation and the incorporation of BIAS VCC. • Medium-drive devices are either three or five digits. High-drive devices have the "9" removed and are four digits long to conform to the prior BTL/FB+ high-drive device-naming convention.
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SCEA019 - January 2001 UBT devices can be used for many different logic functions, reducing the number of different devices you have to buy. This reduces the number of other types of devices that must be maintained in inventory. Ordering larger quantities of UBT devices can reduce the price. However, simpler functions normally are less expensive. Backplane applications usually require only bus-transceiver functionality. Other applications might need more complex functions.
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SCEA019 - January 2001 19 I need an alternate source. Are there any? Several companies manufacture GTL and GTLP devices. Fairchild (FSC) entered the market in 1997. Pericom and Philips also recently entered the market. Pericom’s two released offerings closely match the FSC GTLP data-sheet specifications, and it is assumed that their other planned offerings will also. Philips markets their GTL devices toward the bus on the card/microprocessor interface market much like TI’s existing GTL family.
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SCEA019 - January 2001 20 Are the alternate-source devices identical? While all GTLP devices operate in the same manner and have the same pinout and functionality, they are not all designed equally. The most important characteristic in GTLP devices is the B-port OEC circuitry and the corresponding edge rate. Faster edges perform poorly in backplane.
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SCEA019 - January 2001 21 What is important about live insertion? Many backplane systems in communications applications must remain operational 24 hours a day, 7 days a week. These systems cannot be shut down when a board is inserted or removed from the system, as frequently happens during regular maintenance or system upgrades, nor can active backplane data be disturbed. GTLP devices fully support live insertion with Ioff, PU3S, and BIAS VCC circuitry.
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SCEA019 - January 2001 22 What is the total power consumption of an 18-bit GTLP driver? When you look at backplane performance, you must take into consideration static drive and dynamic drive. The static output drive is the current needed to maintain a steady-state dc voltage level on an output. Dynamic output drive is the current available when an output switches output states. This drive is necessary to overcome reactive loading effects and can determine the switching speeds in your applications.
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SCEA019 - January 2001 PSTAT = 0.5 × 0.5 × VCC (ICCL + ICCH) + 0.5 × VCC (ICCL) = VCC (0.75 × ICCL + 0.25 × ICCH) ICCL, ICCH, and ICCZ are identical for CMOS devices, but different for BiCMOS/bipolar devices. Normally, these are combined in CMOS-device data sheets, but, because both the GTL and GTLP families include both CMOS and BiCMOS devices, all values are included to preclude questions about whether all values are the same or only the maximum value was included.
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SCEA019 - January 2001 ICC = 50 mA, VTT = 1.5 V, VOL = 0.55 V, and RTT = 38 Ω PSTAT = VCC (0.75 × ICCL + 0.25 × ICCH) = 3.3 V (0.75 × 50 mA + 0.25 × 50 mA) = 165 mW IOL = (VTT – VOL) / (RTT / 2) = (1.5 V – 0.55 V) / (38 Ω / 2) = 50 mA POUT switching = IOL × VOL × (1 – output duty cycle) = 50 mA × 0.55 V × (1 – 0.5) = 13.75 mW/bit POUT static low = IOL × VOL × (1 – output duty cycle) = 50 mA × 0.55 V × (1 – 0) = 27.5 mW/bit There are nine switching outputs and nine static low outputs, therefore: POUT = 13.
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SCEA019 - January 2001 23 How should I generate the termination voltage? GTLP backplanes require a high-current 1.5-V termination voltage that typically is driven from the 3.3-V VCC. Typically, a 1.5-V, 7.5-A switcher provides the 1.5-V reference voltage. Currently, TI uses the LT1083CP (Linear Tech) for bus termination on our 48-bit high-drive SN74GTLPH1655 demonstration backplane.
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SCEA019 - January 2001 24 Why not use Thevenin voltage dividers for termination? Thevenin voltage dividers can be used as a termination scheme; resistors are easy to obtain and can be connected to the readily available 3.3-V power supply. However, this is not the optimal termination scheme. There are several reasons why voltage regulation is essential on GTLP backplanes: • Static dc current through the termination - A Thevenin equivalent of two 50-ohm resistors to 3.
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SCEA019 - January 2001 25 Tell me more about bus hold. All GTLPH devices have bus hold on the A port and are described in the data sheet as “Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.” However, a note in the data sheet states “All unused inputs of the devices must be held at VCC or GND to ensure proper operation.
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SCEA019 - January 2001 28 What do I do with unused or undriven GTLP A- or B-port I/Os? As with any other logic device, it is important that unused or undriven inputs or inputs/outputs (I/Os) not be left floating. This prevents high current flow through the device if the input should reach the threshold level. There is no need to prevent the transistor outputs from floating as long as its input is tied to VCC or GND.
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SCEA019 - January 2001 29 Can I connect the SN74GTLPH16612GR unused I/O pins of the A ports and B ports directly to GND? I have seen FSC’s reference design and the unused pins were connected directly to ground. Per the GTLP FAQ, we cannot do that because there should be a resistor for safety purposes. The A ports and B ports can be connected directly to GND on unused pins. Historically, there has always been a resistor used when tying the pin to VCC or GND because it is required for bipolar inputs.
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SCEA019 - January 2001 31 What is the transistor count for GTLP devices? Table 9.
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SCEA019 - January 2001 32 Can I use GTLP as a low-voltage translator? Bidirectional voltage translations between 3.3-V LVTTL and low-voltage CMOS (LV-CMOS) are possible with GTLP devices. GTLP has a larger noise margin than general LV-CMOS interface devices and can support shift-up level conversion through the use of active transistors. Two things must be considered: • In the A-to-B (LVTTL to LV-CMOS) direction, Vref must be within 0.6 V of the termination voltage because of the TI-OPC circuitry.
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SCEA019 - January 2001 Table 10. Bidirectional or Unidirectional B-to-A Voltage Translations LV-CMOS Device GTLP Device Supply Voltage (VCC) Threshold Set Point (Vt) Set Vref To 2.5 V 1.25 V 1.9 V 1.8 V 0.9 V 1.2 V 1.5 V 0.75 V 0.9 V 1.2 V 0.6 V 0.6 V 1.0 V 0.5 V 0.5 V 0.8 V 0.4 V 0.4 V Table 11 shows possible voltage-translation combinations and recommended GTLP device Vref settings for the unidirectional B-to-A case where TI-OPC circuitry is inactive.
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SCEA019 - January 2001 33 What is the voltage input range I can apply to the B port if Vref is set at 0.8 V? I’m using the SN74GTLP1394 to convert a 1.2-V GTL and 1.5-V CMOS signal to LVTTL. Signal direction always is B to A. Vref is set at 0.8 V. I’m concerned that the 1.5-V CMOS signal will be too high and that it will forward-bias ESD diodes on the B-port input. GTLP devices can be used over a range of VTT and Vref voltages and this application is perfectly acceptable, with no danger to the ESD diodes.
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SCEA019 - January 2001 FB+ devices have a fixed differential input set at 1.55 V, whereas GTLP devices have a variable differential input that is set via the external Vref control pin. GTLP Vref is normally two-thirds of the termination voltage so that when VTT is 1.5 V, Vref is 1.0 V. When GTLP devices are used in FB+ device applications, the resistor network is changed to R/3R so that Vref is set at 1.575 V when VTT is 2.1 V.
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SCEA019 - January 2001 What are the advantages and disadvantages? There is excellent signal integrity at higher frequencies, pullup-resistor termination draws less power than totem-pole devices, there is no danger of bus contention on open-drain devices, and the BIAS VCC pin provides for live insertion. The cost is two to three times higher than FCT or LVT, but, because these TIER-3 solutions didn’t work, you need to move to a TIER-2 solution.
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SCEA019 - January 2001 36 How do I get a GTLP data sheet? GTLP product-preview data sheets, GTL production data sheets, and GTL1655/backplane design application reports are in the GTL/GTLP Logic High-Performance Backplane Drivers product information book, literature number SCED009, which can be ordered at http://www.ti.com/sc/gtlpbook or by calling the literature fulfillment center at 1-800-477-8924.
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SCEA019 - January 2001 39 How do I get HSPICE Models? TI has pioneered new modeling technology and will offer encrypted Level-37 HSPICE models that can be downloaded directly from the internet without a confidentiality agreement. Encrypted HSPICE models for all GTLP devices will be available directly from the IBIS home page. HSPICE models provide better device modeling capability than IBIS models. Generally, HSPICE is used for device simulation and IBIS is used for integrated board-level simulation.
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SCEA019 - January 2001 43 If the file is encrypted, why do we need the one-time patch from Avant!? Level 37 is a model TI created to work under HSPICE. Avant! licenses Level 37 to TI and requires TI to provide authorization to distribute the Level-37 model. This method gives TI and Avant! legal protection. The Level-37 patch is required, regardless of whether or not the model is encrypted. The license process requires that: • TI customer must have their own copy of Avant! HSPICE.
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SCEA019 - January 2001 Device symbolization is explained on the Texas Instruments SLL Logic Package Options page at http://www.ti.com/sc/package under Symbolization Guidelines. Package case assignment is found on the Package Name Rule Assignments page at http://www.ti.com/sc/docs/products/logic/package/pkrule.htm Case A, B, and C symbolization names can be found on the Device Name Rules page at http://www.ti.com/sc/docs/products/logic/package/namerule.
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SCEA019 - January 2001 47 How can I request additional technical support? These and other helpful application reports to be released in the future are at http://www.ti.com/sc/docs/apps/logic/appnotes.
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Understanding Advanced Bus-Interface Products SCAA029 May 1996 7–125
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IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty.
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Contents Title Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–131 Device Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ABT Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents (continued) Title Page Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–170 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–171 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Illustrations (continued) Figure Title Page 34 Skew = |tPLH3 – tPLH4| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–165 35 Typical Skew Between Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–165 36 Typical Bus-Hold Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 562
Introduction The purpose of this application report is to assist the designers of high- or low-performance digital logic systems in using the Advanced System Logic (ASL) families: LV, LVC, LVT, ALVC, ABT, ABTE, ALB, GTL, FB, and CBT. A family introduction, followed by a detailed comparison of the electrical characteristics, is provided to help designers understand the differences between these products.
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FB Family The Futurebus (FB)-series devices are used for high-speed bus applications and are fully compatible with the IEEE 1194.1-1991 (BTL) standard. These transceivers are available in 7-, 8-, 9-, and 18-bit versions with TTL and BTL translation in less than 5-ns performance. Other features include drive up to 100 mA and bias pins for live-insertion applications.
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Detailed Comparison The major subject areas covered in this application report are: • • • • • • • • • • • • • Input characteristics Maximum input slew rate Output characteristics (drive capability) 5-V tolerant inputs/outputs Power consideration Package power dissipation Output capacitance ac characteristics Advanced packaging Bus hold Partial power down and live-insertion capability Power-up and power-down high impedance Additional design considerations for GTL and BTL/FB The characterization informatio
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5V VCC 4.44 V VOH 3.5 V VIH 2.5 V VT 5V 2.4 V 2V 1.5 V VIL 1.5 V VCC VOH 5V 2.4 V VOH VT 1.6 V 1.5 V 1.4 V 0.8 V VIL VOL 0.4 V VOL 0.4 V 0V GND 0V GND 0V 5-V TTL, ABT 3.3 V VCC 2.4 V VOH 2V VIH 0.5 V 5-V CMOS Rail-to-Rail 5 V VCC VIH VT VIL 1.5 V VIH VT 2.1 V VOH 1.62 V 1.55 V 1.47 V VIH VT VIL VOL 0.8 V VIL VOL 0.4 V VOL 1.2 V 0.86 V 0.8 V 0.75 V 0.4 V GND 0V GND 0V ETL (ABTE) Larger Noise Margins LVTTL, LVT, LVC, ALVC, LV 1.
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VCC ABT Input D1 Q1 VCC CBT Input Qp Qp OE VIN Qn Qn A ABT INPUT STAGE B CBT INPUT STAGE Figure 2. Typical Input Cell for 5-V Families VCC LV Input VCC LVC/LVT/ALVC Input Qp Qp VIN VIN Qn Qn 5-V-TOLERANT INPUT STAGE (LVC/LVT/ALVC) NON-5-V-TOLERANT INPUT STAGE (LV) Figure 3. Typical Input Cell for 3.3-V Families Supply Current vs Input Voltage 10 TA = 25°C, VCC = 5 V, One bit is driven from 0 V to 6 V I CC – Supply Current – mA 9 8 7 6 5 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
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Table 1. Input Transition Rise or Fall Rate as Specified in Data Sheets recommended operating conditions MIN MAX ABT octals, FB (A port) ∆t /∆v Input transition rise or fall rate† UNIT 5 ABT Widebus, Widebus+ 10 LVT, LVC, ALVC, GTL (A port) 10 LV ns/V 100 † Unless otherwise noted in data sheets Figure 5 shows the input characteristic impedance of both 3.3-V and 5-V families.
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VCC ABT Output D1 R1 R2 Q3 M1 VOUT Q4 ABT OUTPUT STAGE Figure 6. Typical Output Cell for 5-V Families Figure 7 shows a simplified LVT output and illustrates the mixed-mode capability designed into the output stage. This combination of a high-drive TTL stage, along with the rail-to-rail CMOS switching, gives the LVT series exceptional application flexibility. These parts have the same drive characteristics as 5-V ABT devices and provide the dc drive needed for existing 5-V backplanes.
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CMOS Output Characteristics (ALVC, LVC, and LV) Figure 7 also shows a simplified LV, LVC, and ALVC output stage. LV and ALVC are pure 3.3-V families. They cannot be used to translate between 5-V and 3.3-V environments. ALVC is currently the fastest CMOS logic available. It is used primarily for high-speed memory and point-to-point applications with medium drive capability (±24 mA). LV is designed for low-speed, low-drive (±8–6 mA) applications. It is similar to HC and HCT.
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3.3-V Families 3.2 2.8 2.4 TA = 25°C, VCC = 3.3 V, VIH = 3 V, VIL = 0 V VOH – V 2 LVT2 1.6 LVC LVT 1.2 LV 0.8 ALVC 0.4 0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 –30 –20 –10 0 IOH – mA 5-V Families 4 3.6 3.2 TA = 25°C, VCC = 5 V, VIH = 3 V, VIL = 0 V ABTE VOH – V 2.8 ABT 2.4 2 1.6 1.2 ABT2 0.8 0.4 0 –100 –90 –80 –70 –60 –50 –40 IOH – mA Figure 9. Output-High Characteristic Impedance of 3.
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V VIH(min) VIL(max) A B C Figure 10. Reflected-Wave Switching Using typical VOH and VOL values, along with data points from the curves, one can calculate the typical impedance the device can drive. For example, an ABT device can typically drive a line (from either end) in the 25-Ω range on the incident wave. However, if the same line is driven from the middle, the effective impedance seen by the driver is half its original value (12.5 Ω), which requires more current to switch it on the incident wave.
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GTL Input GTL Output VCC VCC BIAS Voltage VREF BIAS Voltage VIN VOUT GTL B-PORT INPUT AND OUTPUT STAGE BTL/FB Input VCC BTL/FB Output VCC VOUT VIN VREF BTL/FB B-PORT INPUT AND OUTPUT STAGE Figure 11.
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Input Characteristic Impedance 10 BTL/FB –10 I IN – mA GTL –30 –50 TA = 25°C, VCC = 5 V, VIH = 3 V, VIL = 0 V –70 –90 –1 0 1 2 3 4 5 6 VIN – Input Voltage – V Output Characteristic Impedance TA = 25°C, VCC = 5 V, VIH = 3 V, VIL = 0 V 2.8 2.4 VOL – V 2 1.6 1.47-V VIL (GTL/FB) 1.2 BTL/FB 0.85-V VIL (GTL) 0.8 GTL 0.4 0 0 25 50 75 100 125 150 175 200 225 250 275 300 IOL – mA Figure 12.
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Power Consumption Several factors influence the power consumption of a device: frequency of operation, number of outputs switching, load capacitance, number of TTL-level inputs, junction temperature, ambient temperature, and thermal resistance of the device. The maximum operating frequency is limited by the thermal characteristics of the package. TI provides package power-dissipation information in data sheets under “absolute maximum ratings”.
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Single-Output Switching Power Consumption 3.3-V Families 30 TA = 25°C, VCC = 3.3 V, VIH = 3 V, VIL = 0 V, No load I CC – Supply Current – mA 25 ALVC 20 LVC LVT 15 LVT2 10 5 LV 0 0 10 20 30 40 50 60 70 80 90 100 Frequency – MHz Single-Output Switching Power Consumption 5-V Families 80 TA = 25°C, VCC = 5 V, VIH = 5 V, VIL = 0 V, No load I CC – Supply Current – mA 70 60 ABT2 ABT 50 40 ABTE 30 20 10 CBT 0 0 10 20 30 40 50 60 70 Frequency – MHz Figure 13.
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All-Outputs Switching Power Consumption 3.3-V Families 250 TA = 25°C, VCC = 3.
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All-Outputs Switching 325 TA = 25°C, VCC = 5 V, VIH = 3 V, VIL = 0 V TA = 25°C, VCC = 5 V, VIH = 3 V, VIL = 0 V 300 275 I CC – Supply Current – mA I CC – Supply Current – mA Single-Output Switching 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 GTL FB 250 225 200 175 FB 150 125 100 GTL 75 50 25 0 0 0 10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100 Frequency – MHz Frequency – MHz Figure 15.
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Power Calculation When calculating the total power consumption of a circuit, both the static and the dynamic currents must be taken into account. Both bipolar and BiCMOS devices have varying static-current levels, depending on the state of the output (ICCL, ICCH, or ICCZ), while a CMOS device has a single value for ICC. These values are given in the individual data sheets.
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BiCMOS Note: ∆ICC = 0 for bipolar devices.
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24-pin SOIC 24-pin SOIC Area = 165 mm2 Height = 2.65 mm Volume = 437 mm3 Lead pitch = 1.27 mm 24-pin SSOP 24-pin SSOP Area = 70 mm2 48-pin SSOP 48-pin SSOP Area = 171 mm2 Height = 2.74 mm Volume = 469 mm3 Lead pitch = 0.635 mm 100-pin SQFP 100-pin SQFP and 100-pin cavity TQFP Area = 266 mm2 Height = 1.1 mm Volume = 119 mm3 Lead pitch = 0.5 mm Height = 1.5 mm Volume = 399 mm3 Lead pitch = 0.
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Table 2. ΘJA for Different Packages NO. OF PINS SOIC SSOP TSSOP QFP TQFP TQFP HP TQFP–HP 14 16 20 24 48 52 56 64 80 100 Package D D DW DW –– –– –– –– –– –– ΘJA 76 73 59 56 –– –– –– –– –– –– Package DB DB DB DB DL ΘJA 185 175 164 152 80 DL 68 Package PW PW PW PW DGG DGG ΘJA 195 187 143 140 115 92 Package RC PH ΘJA 69 84 Package PM PN ΘJA 96 89 PZ 79 Package PCA ΘJA 52.
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8 Bit 16 Bit 8 Bit 1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC 4Y1 4Y2 GND 4Y3 4Y4 4OE 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 2OE 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 VCC 4A1 4A2 GND 4A3 4A4 3OE Figure 18.
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Output Capacitance TI designed both the CMOS and BiCMOS logic families for the lowest capacitance possible. GTL and BTL/FB, however, were designed to meet a 5-pF I/O capacitance on the B port. Figure 20 shows the typical input, I/O, and output capacitance of these families. Input Capacitance 15 13.5 Capacitance – pF 12 10.5 9 TA = 25°C, VCC = 5 V (5-V families), VCC = 3.3 V (3.3-V families), VIH = 3 V, VIL = 0 V, All unused inputs are biased low 9.5 6 4.5 3 1.
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ac Performance Simultaneous-Switching Phenomenon System designers are frequently concerned with the performance degradation of ICs when outputs are switched. TI’s priority, when designing the bus-interface families, is to minimize signal-integrity concerns and reduce the need for excess settling time of an output waveform. This section addresses the simultaneous switching performance of these families for both octals and Widebus devices.
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A similar phenomenon occurs with respect to the VCC plane on a low-to-high transition, known as voltage output high, peak or valley (VOHP, VOHV). Most problems are associated with a large VOLP because, in most cases, the range for a logic 0 is much less than the range for a logic 1 (see Figure 23). For a comprehensive discussion of simultaneous switching, see the Simultaneous Switching Evaluation and Testing application report or the Advanced CMOS Logic Designer’s Handbook from TI.
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The current through an output is dependent on the voltage level and the load seen at the output. This can be expressed mathematically as: i + Cǒdv outńdtǓ (13) Analysis of equations 12 and 13 clearly shows that the more VCC and ground pins there are, the lower the lead inductance, resulting in less noise. As the speed of today’s circuits increases, di/dt increases and so does the generation of simultaneous-switching noise.
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GTL/BTL Output Voltage Peak 1.2 VOLP – V 1 0.8 0.6 0.4 0.2 0 ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÍÍÍÍÏÏÏÏ ÏÏÏÏ ÍÍÍÍ ÍÍÍÍÏÏÏÏ GTL BTL 2 1.8 1.6 1.4 0.75-V VIL (GTL) VOHV – V 1.4 GTL/BTL Output Voltage Valley 1.47-V VIL (FB) 1.2 1 0.8 0.6 0.4 0.2 0 ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÍÍÍÍÏÏÏÏ ÍÍÍÍÏÏÏÏ ÏÏÏÏ ÍÍÍÍ ÏÏÏÏ ÍÍÍÍ ÏÏÏÏ ÍÍÍÍ ÍÍÍÍÏÏÏÏ GTL BTL TA = 25°C, VCC = 5 V (BTL, GTL), VCC = 3.3 V (GTL), VIH = 3 V, VIL = 0 V, Standard load Figure 26.
PAGE 588
Slew Rate Slew rate plays an important role in backplane or point-to-point application designs. The slower the output slew rate of a device, the less susceptible the signal is to reflections and noise. Based on this data, a designer knows how to terminate a bus or backplane. Using the characterization laboratory boards, the output slew rate (trise and tfall) was taken with and without the standard output load.
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Rise Time 3.3-V and 5-V Families 3.3 2.7 Rise Time – ns 2.4 2.1 1.8 1.5 1.2 0.9 0.6 0.3 0 LV LVC LVT ÁÁÁ ÁÁÁ ÁÁÁ ÎÎÁÁÁ ÂÂÂ ÁÁÁ ÈÈÎÎ ÁÁÁ ÂÂÂ ÎÎ ÍÍÍ ÂÂÂ ÈÈÎÎÁÁÁ ÂÂÂ ÍÍÍ ÈÈÎÎÁÁÁ ÂÂÂ ÍÍÍ ÈÈÎÎÁÁÁ ÂÂÂ ÍÍÍ ÈÈÎÎÁÁÁ ÂÂÂ ÍÍÍ ÈÈÎÎÁÁÁ TA = 25°C, VCC = 5 V (5-V families), VCC = 3.3 V (3.3-V families), VIH = 3 V, VIL = 0 V, All unused inputs are biased low, Standard load 3.3-V Families 3 LVT2 ALVC ABT 5-V Families ABT2 ABTE GTL FB CBT† Fall Time 3.3-V and 5-V Families 3.3 3 2.7 Fall Time – ns 2.4 2.
PAGE 590
Rise Time vs No. of Outputs Switching 3.3-V Families 5.5 Rise Time – ns 4.5 TA = 25°C, VCC = 3.3 V, VIH = 3 V, VIL = 0 V, Frequency = 10 MHz, Standard load LV 3.5 ALVC 2.5 LVT2 LVC LVT 1.5 0 2 4 6 8 10 12 14 16 No. of Outputs Switching Rise Time vs No. of Outputs Switching 5-V Families ABTE CBT† 2.5 ABT Rise Time – ns ABT2 FB TA = 25°C, VCC = 5 V, VIH = 3 V, VIL = 0 V, Frequency = 10 MHz, Standard load 1.5 GTL 0.5 0 2 4 6 8 10 12 14 16 No.
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Fall Time vs No. of Outputs Switching 3.3-V Families TA = 25°C, VCC = 3.3 V, VIH = 3 V, VIL = 0 V, Frequency = 10 MHz, Standard load 4 Fall Time – ns LV 3 LVT2 LVC ALVC 2 LVT 1 0 2 4 6 8 10 12 14 16 No. of Outputs Switching Fall Time vs No. of Outputs Switching 5-V Families Fall Time – ns 2.5 TA = 25°C, VCC = 5 V, VIH = 3 V, VIL = 0 V, Frequency = 10 MHz, Standard load CBT† ABTE FB ABT 1.5 ABT2 GTL 0.5 0 2 4 6 8 10 No.
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Effects of Simultaneous Switching and Capacitive Loading on Propagation Delay Another factor that may be of concern to a designer is the change in propagation delay when more outputs are switching or when the output capacitive load is varying. This data is very useful, since a typical application would use all outputs simultaneously. In addition, it usually requires different loading conditions than the data sheet specifies.
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Propagation Delay Time vs No. of Outputs Switching 3.3-V Families 9 TA = 25°C, VCC = 3.3 V, VIH = 3 V, VIL = 0 V, Frequency = 10 MHz, Standard load LV Propagation Delay – ns 8 7 6 5 4 LVC LVT2 LVT 3 ALVC 2 0 2 4 6 8 10 No. of Outputs Switching 12 14 16 Propagation Delay Time vs No. of Outputs Switching 5-V Families FB Propagation Delay – ns 4 ABT 3 ABT2 GTL ABTE TA = 25°C, VCC = 5 V, VIH = 3 V, VIL = 0 V, Frequency = 10 MHz, Standard load 2 1 CBT† 0 0 2 4 6 8 10 No.
PAGE 594
Typical tPHL vs Capacitive Load 3.3-V Families 12 TA = 25°C, VCC = 3.
PAGE 595
Typical tPLH vs Capacitive Load 3.3-V Families 12 TA = 25°C, VCC = 3.
PAGE 596
Skew Skew is a term that is used to define the difference in time between two different signal edges. There are several different types of skew currently being used; however, the skew discussed here is the skew of propagation delays across the outputs of a device. More specifically, it is the difference between the largest value obtained for a propagation delay and the smallest value across all of the outputs.
PAGE 597
Bus-Hold Circuit The most effective method to provide defined levels for a floating bus is to use TI’s bus hold as a built-in feature on selected families (see Table 3). Table 3.
PAGE 598
Partial Power Down Partial power down and live insertion are becoming a major issue in today’s system designs. Many new standards have included this as part of their specification. The plug-and-play feature is beginning to dominate the PC market and the telecom industry has been using it for a long time. When a system is partially down, the unpowered device is expected to go into a high-impedance state so the device does not disturb or disrupt the data on the bus.
PAGE 599
Power-Up or Power-Down High Impedance Power-up 3-state circuitry is another feature that TI offers on selected LVT, ABT, and FB. This feature keeps the output in a high-impedance state during power up or power down, regardless of the output-enable control pin’s state (VCC = 0 V to 2.1 V for ABT and FB, and VCC = 0 V to 1.5 V for LVT). After VCC reaches the specified value, the output-enable control takes over and puts the device in the required state (see Figure 39).
PAGE 600
ABTE, FB, and CBT (CBT6800 only) have an added feature called BIAS VCC. This feature is used to precharge the output, trace, and connector capacitance during power up. This circuit prevents the device from spiking the backplane and disrupting the data during hot-card insertion. For this feature to work, both ground and BIAS VCC pins must make contact before VCC does (both pins should be the longest on the card).
PAGE 601
Conclusion Today’s high-speed bus and point-to-point applications require devices that can provide high performance, excellent signal integrity, and cost effectiveness. TI’s Advanced System Logic (ASL) group offers the widest selection of logic families that meet these requirements, from low drive (6 mA) to high drive (180 mA) and from low performance (16 ns) to high performance (sub 2 ns) propagation delay.
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Acknowledgment The author of this document is Ramzi Ammar. References 1 Texas Instruments Advanced BiCMOS Data Book 1994, SCBD002B. 2 Gunning, Bill; Yuan, Leo; Nguyen, Trung; Wong, Tony, GTL: “A Low-Voltage Swing Transmission-Line Transceiver”, March 15, 1991. 3 Texas Instruments, “Package Thermal Considerations”, Advanced BiCMOS Data Book 1994, SCBD002B, page 13-97.
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Implications of Slow or Floating CMOS Inputs SCBA004C February 1998 7–173
PAGE 604
IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty.
PAGE 605
Contents Title Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–177 Characteristics of Slow or Floating CMOS Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–177 Slow Input Edge Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 606
Introduction In recent years, CMOS (AC/ACT, AHC/AHCT, ALVC, CBT, CBTLV, HC/HCT, LVC, LV/LV-A) and BiCMOS (ABT, ALVT, BCT, FB, GTL, and LVT) logic families have further strengthened their position in the semiconductor market. New designs have adopted both technologies in almost every system that exists, whether it is a PC, a workstation, or a digital switch. The reason is obvious: power consumption is becoming a major issue in today’s market.
PAGE 607
16 VCC = 5 V TA = 25°C One Bit is Driven From 0 V to 6 V I CC – Supply Current – mA 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 VI – Input Voltage – V Figure 2. Supply Current Versus Input Voltage (One Input) recommended operating conditions† MIN ABT octals ∆t/∆v Input transition rise or fall rate 10 AHC, AHCT 20 FB 10 10 LVT, LVC, ALVC, ALVT LV-A HC, HCT VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 2 V VCC = 4.5 V VCC = 6 V † Refer to the latest TI data sheets for device specifications.
PAGE 608
Slow Input Edge Rate With increased speed, logic devices have become more sensitive to slow input edge rates. A slow input edge rate, coupled with the noise generated on the power rails when the output switches, can cause excessive output errors or oscillations. Similar situations can occur if an unused input is left floating or is not actively held at a valid logic level.
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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)† PARAMETER TEST CONDITIONS MIN MAX ABT, AHCT VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 1.5 ∆ICC‡ CBT Control inputs VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 2.5 ∆ICC‡ CBTLV Control inputs VCC = 3 3.6 6V V, One input at 3 V, V Other inputs at VCC or GND 750 VCC = 3 V to 3 3.6 6V V, One input at VCC – 0 0.
PAGE 610
Recommendations for Designing More-Reliable Systems Bus Control The simplest way to avoid floating inputs in a bus system is to ensure that the bus always is either active or inactive for a limited time when the voltage buildup does not exceed the maximum VIL specification (0.8 V for TTL-compatible input). At this voltage, the corresponding ICC value is too low and the device operates without any problem or concern (see Figures 2 and 4).
PAGE 611
Solving for R, the equation becomes: R + t 0.4 (3) CT For multiple transceivers on a bus: R + 0.4 t C (4) N Where: C = individual component and trace capacitance N = number of components connected to the bus Assuming that there are two components connected to the bus, each with a capacitance C = 15 pF, requiring a maximum rise time of 10 ns/V and t = 15-ns total rise time for the input (2 V), the maximum resistor size can be calculated: R + 0.4 15 ns 15 pF 2 + 1.
PAGE 612
As mentioned previously in this section, TI offers the bus-hold capability as stand-alone 10-bit and 16-bit devices (SN74ACT1071 and SN74ACT1073) with clamping diodes to VCC and GND for added protection against line reflections caused by impedance mismatch on the bus. Because purely ohmic resistors cannot be implemented easily in CMOS circuits, a configuration known as a transmission gate is used as the feedback element (see Figure 10).
PAGE 613
TI also offers the bus-hold circuit as a feature added to some of the advanced-family drivers and receivers. This circuit is similar to the stand-alone circuit, with a diode added to the drain of the second inverter (ABT and LVT only, see Figure 12). The diode blocks the overshoot current when the input voltage is higher than VCC (VI > VCC), so only the leakage current is present. This circuit uses the device’s input stage as its first inverter; a second inverter creates the feedback feature.
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300 VCC = 3.6 V VCC = 3.3 V VCC = 3 V VCC = 2.7 V 250 I I(hold) – Hold Current – µ A 200 150 100 50 0 –50 –100 –150 –200 –250 –300 0 1 2 3 4 VO – Output Voltage – V I I(hold) – Hold Current – µ A 400 VCC = 5.5 V VCC = 5 V VCC = 4.5 V 250 100 –50 –200 –350 –500 0 1 2 3 4 5 VI – Input Voltage – V Figure 13.
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Figure 14. Driver and Receiver System Driver Switching From High to Low Driver Switching From Low to High 3 3 VCC = 3.3 V TA = 25°C VO – Output Voltage – V VO – Output Voltage – V Receivers: With Bus Hold Without Bus Hold 2 Bus Hold Switched 1 2 Bus Hold Switched 1 Receivers: With Bus Hold Without Bus Hold VCC = 3.3 V TA = 25°C 0 10 20 30 40 50 Time – ns 60 70 0 105 80 110 115 120 125 Time – ns 130 135 140 Figure 15.
PAGE 616
The power consumption of the bus-hold circuit is minimal when switching the input at higher frequencies. Figure 17 shows the power consumed by the input at different frequencies, with or without bus hold. The increase in power consumption of the bus-hold circuit at higher frequencies is not significant enough to be considered in power calculations. Power Plot of the Input With Bus Hold 0 VCC = 5.5 V 10 MHz 20 MHz 40 MHz 50 MHz 2 Power – mW 4 100 MHz 6 8 10 12 14 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.
PAGE 617
Figure 18 shows the data-sheet dc specifications for bus hold. The first test condition is the minimum current required to hold the bus at 0.8 V or 2 V. These voltages meet the specified low and high levels for TTL inputs. The second test condition is the maximum current that the bus-hold circuit sources or sinks at any input voltage between 0 V and 3.6 V (for low-voltage families) or between 0 V and 5.5 V (for ABT). The bus-hold current becomes minimal as the input voltage approaches the rail voltage.
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GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic SCEA003A March 1997 7–189
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IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty.
PAGE 620
Contents Title Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–193 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–193 Advantages of GTL or BTL Over CMOS/TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Introduction This application report examines the requirements for a low-swing interface in high-speed digital systems and how well this need is addressed by two interface standards: backplane Transceiver Logic (BTL) and Gunning Transceiver Logic (GTL). Both interface standards attempt to improve the performance of high-speed digital systems by reducing the difference between the logic high-voltage level and the logic low-voltage level.
PAGE 622
Advantages of GTL or BTL Over CMOS/TTL BTL and GTL were developed to solve the bus-driving problem associated with TTL and to enhance the performance of point-to-point and backplane applications. BTL and GTL also eliminate the need for the extra time required for the TTL signal to settle due to reflection and noise generated when switching.
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VCC VCC Input Stage Bias Voltage VREF Output Stage Bias Voltage VIN VOUT Figure 3. Typical GTL Input and Output Cells BTL Family Input and Output Structure The BTL input receiver is a differential amplifier with one side connected to an internal reference voltage. The threshold is designed with a narrow window (VIH = 1.62 V and VIL = 1.47 V). Unlike GTL, BTL requires a separate supply voltage for the threshold circuit to eliminate any noise generated by the switching outputs.
PAGE 624
Power Consumption Several factors influence the power consumption of a device: frequency of operation, number of outputs switching, load capacitance, number of TTL-level inputs, junction temperature, ambient temperature, and thermal resistance of the device. For BTL and GTL devices, the output power is supplied externally by the output voltage supply (VTT). The maximum operating frequency is limited by the thermal characteristics of the package.
PAGE 625
Simultaneous Switching In a given digital circuit, there is a large change in current over a very short time when multiple outputs switch simultaneously. As this increased current flows through the bond wires and the leadframe, it develops a voltage across the wire’s inductance. This feedback mechanism is known as simultaneous switching noise (SSN). This noise manifests itself as VOL or VOH voltage bounce at the package pin(s).
PAGE 626
TA = 25°C, VCC(5) = 5 V, VCC(3.3) = 3.3 V, VIH = 3 V, VIL = 0 V, VTT = 1.2 V, RTT = 50 Ω VOHP GTL16612 17 Outputs Switching VOHV GND Channel 1 = 500 mV/div, Timebase = 5 ns/div, VOHV = 1.13 V, VOHP = 1.58 V Figure 7. GTL16612 High Output Voltage Peak and Valley Noise on an Unswitched Output TA = 25°C, VCC = 5 V, VIH = 3 V, VIL = 0 V, BIAS VCC = 5 V, BG VCC = 5 V, VTT = 2.1 V, RTT = 33 Ω FB1650 Channel 1 = 500 mV/div Timebase = 5 ns/div VOLV = 0.97 V VOLP = 1.
PAGE 627
Output Capacitance GTL and BTL devices are designed to meet a 5-pF capacitance on their input and output ports (B port). Figure 10 shows the variation of the output capacitance across both processes. TA = 25°C, VCC = 5 V, VIH = 3 V, VIL = 0 V All unused inputs are biased low 10 Capacitance – pF 8 6 4 2 0 GTL MIN GTL MAX BTL MIN BTL MAX B Port Figure 10. Capacitance Variation Across Process Slew Rate Slew rate plays an important role in backplane or point-to-point application designs.
PAGE 628
TA = 25°C, VCC = 5 V, VIH = 3 V, VIL = 0 V, BIAS VCC = 5 V, BG VCC = 5 V, VTT = 2.1 V, RTT = 33 Ω, Frequency = 10 MHz FB1650 1.8 V 1.3 V GND Channel 1 = 500 mV/div, Timebase = 5 ns/div, tf = 1.51 ns (distance between driver and receiver is 10 in.) Figure 11. FB1650 Fall Time Measured Between 1.3 V and 1.8 V TA = 25°C, VCC(5) = 5 V, VCC(3.3) = 3.3 V, VIH = 3 V, VIL = 0 V, VTT = 1.2 V, RTT = 50 Ω, Frequency = 10 MHz 1V GTL16612 0.5 V GND Channel 1 = 500 mV/div, Timebase = 5 ns/div, tf = 2.
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Signal Integrity Figures 15 and 16 show the signal integrity of data propagating across the 50-Ω transmission line using three cable lengths (A = 12 in., B = 28 in., and C = 46 in.). The clock frequency is 75 MHz. The measurement was taken at the receiver end of the cable. The GTL output waveform has kept its input square-wave shape better than the BTL waveform has.
PAGE 630
VTT R VREF 2R C Figure 17. Proposed Circuit to Generate VREF For the BTL family, four power supplies and two grounds are connected. For live-insertion applications, the power-up sequence should be: the GND pin should make contact first, followed by BIAS VCC. This sequence will precharge the board and the device capacitance and will establish a voltage between 1.62 V and 2.1 V on the BTL outputs. Next, the VCC pin makes contact and, as VCC ramps up, the BIAS VCC circuitry starts to turn off.
PAGE 631
Table 3. Typical Strip-Line Characteristics† DIMENSIONS (mils) MAXIMUM NUMBER OF LOADS T H W LINE IMPEDANCE ZO (Ω) 1.5 6 20 27 6.67 1.5 6 15 32 5.83 1.5 10 20 34 5.58 1.5 12 20 37 1.5 10 15 40 1.5 12 15 43 1.5 20 20 1.5 20 15 1.5 30 1.5 30 CAPACITANCE CO (pF/in.) (pF/in ) tpd (ns/in ) (ns/in.) GTL BTL L = 12 in. L = 16 in. L = 24 in. 0.18 10 8 12 0.186 11 9 14 0.189 11 9 14 4.75 0.176 12 11 16 4.67 0.187 13 11 16 4 0.
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Next-Generation BTL/Futurebus Transceivers Allow Single-Sided SMT Manufacturing SCBA003C March 1997 7–205
PAGE 633
IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty.
PAGE 634
Contents Title Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–209 Current Generation of BTL/Futurebus Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–209 A New Generation of BTL/Futurebus Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Introduction BTL (IEEE 1194.1-1991) and Futurebus designs offer significant performance advantages over conventional TTL backplane implementations, but these advantages come with trade-offs. Switching noise in the form of ground bounce and EMI must be controlled, and proper termination schemes must be employed to ensure signal integrity in this high-speed switching environment. Trade-offs for price in the form of total system solution versus overall system performance are also of concern.
PAGE 636
2.1 V Low-to-High and High-to-Low Transition 1V 1 ns Minimum Figure 2. Slew-Rate Control (OEC) Diagram Table 1 shows an evolutionary progression in bipolar wafer-fab technology and improved propagation-delay performance. Bipolar fab technologies are chosen for this class of device for their high drive capability, low switching noise, and relative ease of designing (relative to pure CMOS) the analog circuitry required to meet the slew-rate control requirement (see Figure 2).
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TFB2022 64-Bit Data-Path Unit TFB2002 I/O Controller FB2031* FB2031* FB2031* FB2031* TFB2010 Arbitrator FB2040 FB2031* FB2032 FB2040* 25-mm Stub Length MAX Address/Data Status Command Arbitration Sync Connector NOTE: The second-part type descriptor (*) indicates that a second transceiver is mounted on the opposite side of the board. Figure 3.
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OEB OEB OEA AI1 FB2040 46 45 47 40 51 B1 Split TTL I/Os AO1 50 To Seven Other Channels LCA SEL0 SEL1 LCB OEB OEB OEA 18 FB2031 20 15 16 46 45 1D 47 C1 40 1D C1 A1 MUX 20 1D MUX C1 1D C1 To Eight Other Channels Pin numbers shown are for the RC package. Figure 4.
PAGE 639
A New Generation of BTL/Futurebus Transceivers In response to the need for single-sided surface mounting and simplified transceiver architectures, Texas Instruments has developed both a high-power package and a series of 18-channel BTL/Futurebus universal bus transceivers (UBT). These new devices, designated as the FB16xx series, are packaged in a high-power version of the EIAJ standard 100-pin TQFP package (0.5-mm lead pitch).
PAGE 640
1OEB 1OEB 1CLKAB 1LEAB 1LEBA 1CLKBA 1OEA 1OEA 1AI1 45 46 43 44 41 42 39 40 36 1D C2 C1 Split TTL I/Os 1AO1 37 50 1B1 1D C2 C1 To Eight Other Channels 1OEB 1OEB 1CLKAB 1LEAB 1LEBA 1CLKBA 1OEA 1OEA 1AI1 45 46 43 44 41 42 39 40 36 1D C2 C1 Split TTL I/Os 1AO1 37 1D C2 C1 To Eight Other Channels Pin numbers shown are for the PCA package. Figure 6.
PAGE 641
This flexible design approach eliminates the need for double-sided surface mounting, along with all of the associated manufacturing costs, and still meets the IEEE 896.2-1991 25-mm maximum-stub-length requirement (see Figure 7). TFB2022 64-Bit Data-Path Unit TFB2002 I/O Controller FB16xx FB16xx FB16xx FB16xx TFB2010 Arbitrator FB2032 FB16xx FB16xx 25-mm Maximum Stub Length Address/Data Status Command Arbitration Sync Connector NOTE: There is no double-sided SMT requirement. Figure 7.
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Summary The high-speed data-communication requirements of today’s fastest board-level computers and telecommunications and network switching equipments can be met with BTL- and Futurebus-compatible transceivers and switching levels. Stub-length constraints and ever-increasing data-path widths have made it difficult to control signal integrity and manufacturing and procurement costs in these high-performance systems.
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Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices SCBA006A December 1996 7–217
PAGE 644
IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty.
PAGE 645
Contents Title Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–221 Skews . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–221 Source of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Introduction The data in this application report demonstrates the skew between the outputs of a sample of Texas Instruments Advanced BiCMOS (ABT) devices. This report explains which output skew is being examined, where the data comes from, and how the data is analyzed. Some of the errors that may be present in the data are discussed. Skews Skew is a term that defines the difference in time between two signal edges. Several different types of skew being used are defined in JEDEC 99 clause 2.3.5.
PAGE 647
For those devices (’ABT16952 and ’ABT16500A) that have registers, the data path chosen for each device was the path that put the device in a transparent mode. Also, for the bidirectional devices (’ABT16245, ’ABT16952, and ’ABT16500A), the A-to-B direction was used. 1 2 tPLH14 3 • • • tPLH3 16 Figure 1. Skew = |tPLH14 – tPLH3| Sources of Error in Data The data in this report was taken on an IMPACT tester, which is automatic test equipment used to characterize integrated circuits.
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0.8 0.7 0.7 0.6 0.6 Output Skew – ns 0.8 0.5 0.4 0.3 0.5 0.4 0.3 0.2 0.2 0.1 0.1 0 –55 –40 Output Skew – ns tPHL Average of Output Skews 25 85 0 –55 –40 125 Temperature – °C tPLH Average + 3 σ tPHL Average + 3 σ 0.8 0.8 0.7 0.7 0.6 0.6 0.5 0.4 0.3 85 125 0.3 0.1 0.1 85 125 0.4 0.2 25 85 0.5 0.2 0 –55 –40 25 Temperature – °C Output Skew – ns Output Skew – ns tPLH Average of Output Skews 0 –55 –40 125 Temperature – °C 25 Temperature – °C X – VCC = 4.
PAGE 649
0.8 0.7 0.7 0.6 0.6 Output Skew – ns 0.8 0.5 0.4 0.3 0.5 0.4 0.3 0.2 0.2 0.1 0.1 0 –55 –40 Output Skew – ns tPHL Average of Output Skews 25 85 0 –55 –40 125 Temperature – °C tPLH Average + 3 σ tPHL Average + 3 σ 0.8 0.8 0.7 0.7 0.6 0.6 0.5 0.4 0.3 0.1 125 Temperature – °C 0 –55 –40 25 Temperature – °C X – VCC = 4.5 V Y – VCC = 5 V ±VCC = 5.5 V Figure 3. ’ABT16240 – Simultaneous Switching 7–224 85 125 0.3 0.1 85 125 0.4 0.2 25 85 0.5 0.
PAGE 650
0.8 0.7 0.7 0.6 0.6 0.5 0.5 Output Skew – ns 0.8 0.4 0.3 0.4 0.3 0.2 0.2 0.1 0.1 0 –55 –40 Output Skew – ns tPHL Average of Output Skews 25 85 0 –55 –40 125 Temperature – °C tPLH Average + 3 σ tPHL Average + 3 σ 0.8 0.8 0.7 0.7 0.6 0.6 0.5 0.4 0.3 85 125 0.3 0.1 0.1 85 125 0.4 0.2 25 85 0.5 0.2 0 –55 –40 25 Temperature – °C Output Skew – ns Output Skew – ns tPLH Average of Output Skews 125 0 –55 –40 Temperature – °C 25 Temperature – °C X – VCC = 4.
PAGE 651
0.8 0.7 0.7 0.6 0.6 Output Skew – ns 0.8 0.5 0.4 0.3 0.5 0.4 0.3 0.2 0.2 0.1 0.1 0 –55 –40 Output Skew – ns tPHL Average of Output Skews 25 85 0 –55 –40 125 Temperature – °C tPLH Average + 3 σ tPHL Average + 3 σ 0.8 0.8 0.7 0.7 0.6 0.6 0.5 0.4 0.3 0.1 125 0 –55 –40 Temperature – °C 25 Temperature – °C X – VCC = 4.5 V Y – VCC = 5 V ±VCC = 5.5 V Figure 5. ’ABT16952 – Single Switching 7–226 85 125 0.3 0.1 85 125 0.4 0.2 25 85 0.5 0.
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0.8 0.7 0.7 0.6 0.6 Output Skew – ns 0.8 0.5 0.4 0.3 0.5 0.4 0.3 0.2 0.2 0.1 0.1 0 –55 –40 Output Skew – ns tPHL Average of Output Skews 25 85 0 –55 –40 125 Temperature – °C tPLH Average + 3 σ tPHL Average + 3 σ 0.8 0.8 0.7 0.7 0.6 0.6 0.5 0.4 0.3 85 125 0.3 0.1 0.1 85 125 0.4 0.2 25 85 0.5 0.2 0 –55 –40 25 Temperature – °C Output Skew – ns Output Skew – ns tPLH Average of Output Skews 125 0 –55 –40 Temperature – °C 25 Temperature – °C X – VCC = 4.
PAGE 653
0.8 0.8 0.7 0.7 0.6 0.6 Output Skew – ns 0.5 0.4 0.3 0.5 0.4 0.3 0.2 0.2 0.1 0.1 0 –55 –40 Output Skew – ns tPHL Average of Output Skews 25 85 0 –55 –40 125 Temperature – °C tPLH Average + 3 σ tPHL Average + 3 σ 0.8 0.8 0.7 0.7 0.6 0.6 0.5 0.4 0.3 0.1 125 Temperature – °C 0 –55 –40 25 Temperature – °C X – VCC = 4.5 V Y – VCC = 5 V ±VCC = 5.5 V Figure 7. ’ABT16500A – Simultaneous Switching 7–228 85 125 0.3 0.1 85 125 0.4 0.2 25 85 0.5 0.
PAGE 654
0.8 0.7 0.7 0.6 0.6 0.5 0.5 Output Skew – ns 0.8 0.4 0.3 0.4 0.3 0.2 0.2 0.1 0.1 0 –55 –40 Output Skew – ns tPHL Average of Output Skews 25 85 0 –55 –40 125 Temperature – °C tPLH Average + 3 σ tPHL Average + 3 σ 0.8 0.8 0.7 0.7 0.6 0.6 0.5 0.4 0.3 85 125 0.3 0.1 0.1 85 125 0.4 0.2 25 85 0.5 0.2 0 –55 –40 25 Temperature – °C Output Skew – ns Output Skew – ns tPLH Average of Output Skews 125 0 –55 –40 Temperature – °C 25 Temperature – °C X – VCC = 4.
PAGE 655
1.3 1.3 1.2 1.2 1.1 1.1 1.0 1.0 Output Skew – ns 1.4 0.9 0.8 0.7 0.6 0.5 0.8 0.7 0.6 0.5 0.4 0.3 0.3 0.2 0.2 0.1 0.1 25 85 0 –55 –40 125 25 Temperature – °C tPLH Eight Outputs Switching tPHL Eight Outputs Switching 1.5 1.4 1.4 1.3 1.3 1.2 1.2 1.1 1.1 1.0 1.0 0.9 0.8 0.7 0.6 0.8 0.7 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 25 85 125 0.9 125 Temperature – °C 0 –55 –40 25 Temperature – °C X – VCC = 4.5 V Y – VCC = 5 V ±VCC = 5.5 V Figure 9.
PAGE 656
Application Report SZZA016B - June 2001 Basic Design Considerations for Backplanes Shankar Balasubramaniam, Ramzi Ammar, Ernest Cox, Steve Blozis, and Jose M. Soltero Standard Linear & Logic ABSTRACT This application report describes design issues relevant to the parallel backplanes typically used in the wireless, datacom, telecom, and networking markets.
PAGE 657
SZZA016B List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Point-to-Point Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multipoint Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equivalent Multipoint Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 658
SZZA016B Introduction Since the beginning, most equipment makers have used parallel-backplane architectures to deliver large amounts of data across one shared bus. The parallel backplane provides a physical and electrical interconnect between various modules in a system. Each module in the backplane communicates with other modules through the backplane bus. Typically, this bus is driven by a backplane transceiver, primarily as the point-of-contact between backplane cards.
PAGE 659
SZZA016B The propagation delay (tpd) is the time delay through the transmission line per unit length and is a function of the natural impedance and characteristic capacitance. Use equation 1 to calculate propagation delay (tpd). t pd + Z o Co (1) In this example, tpd = 51 Ω × 3.5 pF/in. (138 pF/m) yields 178.5 ps/in. (7038 ps/m or 7.03 ns/m).
PAGE 660
SZZA016B Distributed Capacitance Figure 3 is a simplified version of Figure 2, where an equivalent capacitive load (12-pF capacitor) replaces the receivers. It is assumed that the spacing between card slots is within the rise and fall time of the driver signal, and that all slots are populated with cards. VTT VTT RTT Tx d = 1 in. or 2.54 cm RTT A B 12 pF 12 pF 12 pF 12 pF 12 pF 12 pF 12 pF 12 pF 12 pF 12 pF l = 10 in. or 25.4 cm Figure 3.
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SZZA016B Two different printed circuit board (PCB) transmission lines are shown in Figure 5. Basically, microstrip resides on the top of the PCB, whereas the stripline is imbedded within the PCB layers. A microstrip is faster due to the less inherent capacitance, but a stripline exhibits better signal integrity because the reference planes shield the conductor from damaging EMI fields. Other performance differences are discussed later in this application report.
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SZZA016B Figures 6 and 7 show the effects of the term Ǹ1 ) ǒCdńCoǓ on Zo and tpd by plotting the normalized effective impedance and tpd in terms of distributed capacitance divided by the characteristic capacitance, Cd/Co. NORMALIZED IMPEDANCE 1 0.9 0.8 Zo(eff)/Zo 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 13 14 15 Cd/Co Figure 6. Effective Impedance vs Cd/Co NORMALIZED tpd 4 3.5 t pd(eff)/ t pd 3 2.5 2 1.5 1 0.
PAGE 663
SZZA016B In a previous example (capacitors in Figure 3), Cd = 12 pF/in. (472 pF/m) and Co = 3.5 pF/in. Ǹ (138 pF/m) make the Cd/Co ratio = 3.43 and the term 1 ) ǒC dńC oǓ = 2.1. Figures 6 and 7 reflect the changes in the effective values of the transmission line to be 0.48 times the normal impedance and 2.1 times the normal propagation delay. Another way to calculate the new effective impedance and propagation delay is to use equations 4 and 5 instead of Figures 6 and 7.
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SZZA016B Optimum Termination Simulation Figure 9 is the result of HSPICE simulation of the circuit in Figure 3, with 51 Ω used for the pullup terminations (RTT) to 1.5 V. Figure 3 did not show the L-C-R values inherent in transmission lines, but they are included in the HSPICE simulations. The transmitter (driver) is a high-drive GTLP device operating at 50-MHz clock frequency. Because the device is operating in the latched mode, the data signal shown is only one-half clock frequency, or 25 MHz. 1.6 1.4 1.
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SZZA016B 1.6 1.4 1.2 Voltage – V Delta X = 3.75 × 10–9 ns Delta X = 3.75 × 10–9 ns 1 0.8 0.6 Receiver (Point B) 0.4 Driver (Point A) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 Time – ns Figure 10. Matched Line Termination Stripline vs Microstrip Tradeoffs Table 1 demonstrates the effects of distributed capacitance on various microstrip and stripline transmission lines used in backplane designs.
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SZZA016B Using the same impedance (Zo) in a loaded backplane, microstrip lines (on the surface of the backplane board) have a faster effective tpd than striplines (embedded in the backplane board), but the microstrips have a lower effective impedance than the stripline. This lower effective impedance requires a lower termination resistance to properly terminate the backplane.
PAGE 667
SZZA016B The dc analysis can help provide the designer with best-case low-level voltage (VOL1) and worst-case (VOL2) signal levels expected at the receivers on a backplane when the termination resistance has been determined. The VOL levels affect the noise margins at all receivers as shown in Figure 10. The signal at point B is at the last receiver at the end of a 10-in.-long transmission line. The low level of this signal is higher than that of point A (less lower noise margin).
PAGE 668
SZZA016B 2.5 Rise Time – ns 2 1.5 S4 1 S3 0.5 S2 0 S4 = Rx (end) S3 = B/P (end) S2 = B/P (start) S1 = Driver S1 25 51 75 Stub Zo – Ω Figure 13. Rise Time vs Stub Zo at Various Points on the Backplane The higher-impedance stubs (higher inductance) produce a faster driver rise time (higher slew rate) and, therefore, faster rise times at all points along the backplane. This shows that system slew rate is dependent on both the device slew rate and the stub impedance.
PAGE 669
SZZA016B The termination was calculated for each stub length, using equation 9. The capacitance of the different stub lengths changed the distributed capacitance on the backplane. Figure 14 shows that as stub length increases, stub delay increases and driver rise time (slew rate) decreases. Figure 15 shows the effect of stub length on termination resistance, and demonstrates that longer stub lengths result in a lower optimum RTT when everything else is held constant.
PAGE 670
SZZA016B 5.3 5.2 t (flight) – ns 5.1 5 Rt = 24 Ω Conn. Zo = 50 Ω 4.9 Rt = 24 Ω Conn. Zo = 25 Ω 4.8 Rt = Calc. Conn. Zo = 50 Ω 4.7 Rt = Calc. Conn. Zo = 25 Ω 4.6 4.5 4.4 0 20 40 60 80 100 Stub Zo – Ω Figure 16. System Flight Time vs Stub Impedance Figure 16 indicates that a range of stub impedances produces a minimum system flight time. Lowest flight times are observed between 35 Ω and 50 Ω.
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SZZA016B Fully Loaded Backplane Figure 17 clearly shows the effect of the different termination resistors on signal integrity in the fully loaded EVM. All waveforms show incident-wave switching, with upper noise margin gained with lower termination-resistor values. The 50-Ω termination value is unacceptable. The 43.5-MHz and 11.5-MHz data waveforms are included for comparison. 10 ns VTT RTT = 25 Ω 1.5 V RTT = 33 Ω VREF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0.28 V/ns 0.42 V/ns 43.
PAGE 672
SZZA016B Ct can be calculated using the information known about the EVM and the observed Zo(eff). Assuming stripline construction with Zo = 95 Ω and Co = 2.40 pF/in, solve for Cd using equation 9 and assuming that the optimum RTT = Zo(eff) = 35 Ω. An interpolated RTT value of 35 Ω was chosen because it produces the best incident-wave switching performance. Then, solve for Ct by multiplying Cd by the separation between two transceivers which, in this case, is 0.94 in.
PAGE 673
SZZA016B 0.5 V/ns VTT 1.5 V VTT 0.31 V/ns RTT = 33 Ω RTT = 38 Ω VREF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 10 ns RTT = 25 Ω 43.5-MHz Data RTT = 50 Ω 10 ns VTT RTT = 33 Ω 0.5 V/ns RTT = 25 Ω VREF 0.33 V/ns RTT = 38 Ω RTT = 50 Ω 25-MHz Data 1.5 V 0.5 V/ns RTT = 25 Ω RTT = 33 Ω VTT 0.33 V/ns RTT = 38 Ω VREF 11.5-MHz Data 25 ns RTT = 50 Ω RTT SN74GTLPH1655DGGR With Edge-Rate Control in Slow Figure 18.
PAGE 674
SZZA016B Very Lightly Loaded Backplane Figure 19 clearly shows the effect of the different termination resistors on signal integrity when every other three cards are removed from the EVM and the distributed capacitive load is reduced by a factor of four. VTT 1.5 V RTT = 25 Ω 0.54 V/ns RTT = 33 Ω RTT = 38 Ω VREF RTT = 50 Ω 43.5-MHz Data 0.4 V/ns 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 10 ns RTT = 33 Ω 10 ns VTT RTT = 25 Ω VREF 0.41 V/ns 0.
PAGE 675
SZZA016B The total capacitance in all the above cases was calculated to be about 14 pF, based on the observed optimum RTT. Analyzing each component in the capacitance chain on the daughter card is summed below, with the results close to observed and measured. The daughter-card construction use for the GTLP EVM is different from the original assumptions. The via and stub 1 add no capacitance to the line.
PAGE 676
SZZA016B Note the difference in the fully loaded trace impedance between trace D1/D7 and the other traces. Using the lower natural trace impedance offers the advantage of a smaller tpd and shorter time of flight, but at the expense of terminating with a lower-value termination resistor and the subsequent increase in power consumption. Texas Instruments offers both medium-drive (50 mA) and high-drive (100 mA) GTLP devices to allow the designer to match the device with backplane loading.
PAGE 677
SZZA016B Backplane DC Effects – Theory to Practice Figure 20 shows the dc effects previously described in the Backplane DC Effects section on a fully loaded backplane with waveforms plotted at different terminations. VOL information is taken with an 8-MHz clock frequency (4-MHz data), which is the slowest crystal oscillator we had on hand, in order to eliminate as much ac switching effects from the VOL measurement as possible.
PAGE 678
SZZA016B Table 4. Theoretical vs Actual VOL Measurements RTT (Ω) THEORETICAL VALUES ACTUAL VALUES VOL SLOT 2 (V) VOL SLOT 20 (V) DIFFERENCE (mV) DIFFERENCE (mV) 25 0.260 0.380 121 120 33 0.207 0.305 98 96 38 0.184 0.271 87 50 0.145 0.215 69 72 Data from Table 4 also implies that there is a theoretical maximum length of a backplane.
PAGE 679
SZZA016B Bibliography Higgs, Mike, 1997. Advanced Schottky Load Management, Texas Instruments application report, SDYA016. Ammar, Ramzi, 1997. GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic, Texas Instruments application report, SCEA003A. Johnson, Howard, and Graham, Martin, 1993. High-Speed Digital Design, Prentice-Hall, Inc.
PAGE 680
Application Report SCEA022 - April 2001 Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP) Johannes Huchzermeier Standard Linear & Logic ABSTRACT This application report compares two approaches for synchronous bus-system designs. The focus of the report is the comparison of a system using central-synchronous system clock (CSSC) with a system operated with a source-synchronous system clock (SSSC).
PAGE 681
SCEA022 List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Ideal Transmission Line With Negligible Conductance and Resistance . . . . . . . . . . . . . . . . . . Additional Capacitive Load of Line by Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effect of Slot Spacing on Line Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effect of Slot Spacing on Flight Time . . . . . . . . . . . . . . . . . . . .
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SCEA022 1 Introduction Driver modules that are set up for a modern-wiring backplane have many complex requirements. The drivers must switch fast, with the smallest possible propagation time and the greatest possible number of bits in one driver, to provide the necessary data throughput over the bus. In addition, the driver should have a sufficiently high driver capacity to generate the required logic levels, even in the case of a full backplane with many interconnected receive and transmit modules.
PAGE 683
SCEA022 2 Physical Properties and Limitations of Bus Lines The basic composition of a line consisting of capacitive and inductive replacement components is shown in Figure 1. In the case of static conditions, line impedance primarily is determined by the ohmic resistance and/or the parallel conductance of C′ of the line. These are not of any consequence at a frequency of just a few kilohertz, because the frequency is in the term ω = 2 × π × f.
PAGE 684
SCEA022 VTT VTT R1 R1 d = 1 inch R2 RTT R2 L0 L0 C0 CL L0 C0 L0 CL RTT C0 CL Figure 2. Additional Capacitive Load of Line by Modules If the distances between the inserted modules remain electrically short, i.e., twice the propagation delay time between two inserted modules is shorter than the rise/fall time of the signal, it is possible to add the capacitive load to the capacitive layer. The influence on the inductive layer is negligible.
PAGE 685
SCEA022 While the inductive layer remains almost constant in all three cases, the connectors, stub lines to the connector, and driver input and output, as well as the input capacity of the receiver, represent an additional capacitive load for the line. The increased capacitive load reduces the line impedance and starts the demand for higher driver capability for bus-interface logic.
PAGE 686
SCEA022 One curve represents a bus line in the unloaded state, for which the bus-side connectors are the only loads on the line. The other curve represents a fully loaded bus line. The same correlation also is produced with regard to the propagation time of the line, and is shown in Figure 4.
PAGE 687
SCEA022 3 Transfer Modes For a synchronous system, as the name suggests, it is important for the transferred data to refer to a common system-clock signal. Every participant in the system then gets the active edge of system clock as a reference and a data signal, which refers to the system clock.
PAGE 688
SCEA022 3.1.1 Skew Skew is the small difference that arises from different propagation delays between output stages within a device. These differences, which cannot be prevented, are defined in the EIA/JEDEC standard, Definition of Skew Specification for Standard Logic Devices (EIA/JESD 65) (see Figure 6). Output-to-Output Skew The maximum difference of the delay between the fastest and slowest output driver within one circuit [tsk(o) ∼ 0.
PAGE 689
SCEA022 3.1.2 Propagation Time Due to Simultaneous Switching The simultaneous switching parameter, ∆tpd, is the difference in propagation time that arises from the simultaneous switching of several outputs of the same device. Data sheets show only the maximum propagation time of one output when it is the only one to be switched. An additional propagation time must be taken into account when multiple outputs are switched simultaneously.
PAGE 690
SCEA022 3.1.3 Setup and Hold Times at Receiver Input In a synchronous system, a common clock signal, which is synchronous for all the interface devices (e.g., registers or flip-flops) exists. Figure 8 shows the definitions for setup and hold time based on a D flip-flop. Both times are defined around the active edge of the clock signal. td Critical Time Window td = 10 . . .
PAGE 691
SCEA022 3.2 Central Synchronous Clock Distribution A basic prerequisite for a synchronous system is that the transferred signals refer to a common clock signal that is transmitted from a central clock distribution circuit. In the layout shown in Figure 9, the active clock edge reaches all parts of the system as simultaneously as possible. For skew adjustment, the line lengths have been chosen to be as close as possible.
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SCEA022 CLK (0) Active Edge CLK (1) Active Edge Time Budget ∆tpd Simultaneous Switching + tsk(o) tpdmax From CLK to B Flight Time Propagation Delay Over Bus Line tsk(clk) Clock Skew Timing Margin For Safe Design, e.g., to Handle Tolerances, etc.
PAGE 693
SCEA022 tclk Clock System Synchronous 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 tpd Sender Data Out D32 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 Case 1: Bus Delay Matches Timing for Central System-Clock Data Transfer tsu Data at Receiver tbus delay Receiver Reads D32 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 < Case 2: Bus Delay Exeeds One Clock Cycle Data at Receiver D32 D1 D2 D3 D4 D5 D6 D7
PAGE 694
SCEA022 3.3 Source-Synchronous Clock Distribution To eliminate the signal propagation delay time on the bus, the solution illustrated in Figure 12 can be used. An additional line for the source-synchronous clock signal and other lines for the arbitration or transmission of the send/receive status are required. However, propagation delay time over the bus (tflight) is eliminated from the calculation of the maximum clock frequency. Therefore, a significantly higher system speed is possible.
PAGE 695
SCEA022 Sender Active Edge (CLK) Received Clocking in Data (D1) Sender Active Edge (CLK) Received Clocking in Data (D2) Period = 1/fclock Receiver Active Edge (CLK) Received Clocking in Data (D1) Sender Active Edge (CLK) Transmitted Timing Margin tpdmax From CLK to B tsk(clk) Clock Skew Flight-Time Data Propagation Delay Over Bus Line tsetup t∆OUT thold t(rec) t(sender) Sender In Sender Out Sender Clocks in D1 Flight-Time Clock D1 D2 Dn D1 Don’t Care Sender Clocks in D2 Dn+1 Dn–1 Dn D
PAGE 696
SCEA022 tclk Sender Clock Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 tpd Sender Data Out D32 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Sender Clock Out 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D16 D17 16 D18 17 18 t∆out tbus delay Case 1: Bus Delay Matches Timing for Central System-Clock Data Transfer Receiver Data In D32 D1 D2 D3 D4 D5 D6 D7 D8 D9 Receiver Clock Input 0 1 2 3 4 5 6 7 8 9 tdata clock tbus delay
PAGE 697
SCEA022 4 Measurements Using Texas Instruments GTLP Evaluation Module Theoretical considerations concerning the two transmission modes discussed in the previous sections can be confirmed by measurements, using the GTLP demonstration backplane. The evaluation module (EVM) (see Figure 15) is a good model for a typical parallel-backplane system as found, for example, in telecom applications. Figure 15.
PAGE 698
SCEA022 LVTTL Monitor Points TP8 TP7 JB1 No. 1 Bit Not Switch Selection JB3 Slow/Fast Edge-Rate Selection TP1 TP2 TP3 TP4 GTLPH1655 A Port = LVTTL Data I/O TP5 B Port = GTLP Data I/O TP6 GTLP1394 Vref Resistors and Bypass Capacitor JB2 Source-Synchronous Clock Selection AMP Through-Hole Connector Figure 16. Layout of Driver Card With Monitor Points and Jumpers Figure 17 shows a receiver card.
PAGE 699
SCEA022 The EVM is used to illustrate the difference between system-synchronous data transfer and source-synchronous data transfer. The transmitter is at the beginning of the bus line, and the receiver is at the end of the bus. In both cases, 66 MHz is the clock speed, and gives a clock period of 15.15 ns. 4.1 Data Transfer With System-Synchronous Clock The propagation time of the signal via the bus amounts to about 4 ns, if all other slots are empty.
PAGE 700
SCEA022 Therefore, the required period in this case is 21 ns, increasing the chosen clock period from 66 MHz by 6 ns. The consequence is that not all modules receive the same data with the same clock edge. Some modules receive the data with the active edge of consecutive clock periods, as shown in Figure 19. With an empty backplane (see Figure 18), the data was transmitted with the next active edge of the clock signal at the receiver output. In this case, it takes one more clock period (see Figure 19).
PAGE 701
SCEA022 4.2 Data Transfer With Source-Synchronous Clock The sender is switched to source-synchronous clock mode by moving a jumper on the driver card. Comparing the signals on the empty backplane, there is little difference, as similar results are seen in the oscilloscope pictures (see Figure 16). In the source-synchronous mode, the signal is within the same clock period (see Figure 20).
PAGE 702
SCEA022 Volts, 0.5 V/Div FULLY LOADED BACKPLANE AT 66 MHz, RTT = 38 Ω, ERC = VCC 0 ns 25 ns 50 ns 75 ns 100 ns 125 ns 150 ns 175 ns 200 ns 225 ns 250 ns 275 ns 300 ns Propagation Time, 25 ns/Div GTLP Bus Begin GTLP Bus End Receiver Clock Receiver Out LVTTL Figure 21. Fully Loaded Backplane, SSSC, Transmitter in Slot 1, Receiver in Slot 20 Even if the bus is fully loaded, a correct signal transfer can be observed. The only drawback is the need for an additional line in the bus layout.
PAGE 703
SCEA022 5 Summary With the central-clock-distribution system, the highest possible system pulse rate is about 50 MHz (assuming a 19-inch backplane). With the source-synchronous system, the clock frequency can be increased by a factor of 2.4, to 120 MHz. Table 2 lists three system solutions, along with relevant parameters that must be taken into account during system design. Table 2.
PAGE 704
SCEA022 6 Glossary BTL Backplane transceiver logic CMOS Complementary symmetry metal-oxide semiconductor CSSC Central-synchronous system clock DUT Device under test FB FutureBus (device identifier for backplane transceiver logic devices) GND Ground GTLP Gunning transceiver logic plus I/O Input/output LVTTL Low-voltage transistor-transistor logic with 3.
PAGE 705
SCEA022 7 Bibliography Electronic Industries Alliance Definition of Skew Specifications for Standard Logic Devices, EIA/JESD65, September 1998. Interference Control Technologies, Inc. Donald R. J. White, EMI Control in the Design of Printed Circuit Boards and Backplanes. Texas Instruments Incorporated G. Becke, E. Haseloff, Das TTL-Kochbuch (The TTL Cookbook), SDYZG17. PCB Design Guidelines for Reduced EMI, Application Report, November 1999, SZZA009.
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Application Report SCEA017 - April 2001 GTLP in BTL Applications Steve Blozis Standard Linear & Logic ABSTRACT This application report addresses the issues a designer might face when using a GTLP device in a BTL/FB+ application when a legacy BTL/FB+ bus implementation is still in use. Key BTL/FB+ and GTLP device characteristics are compared, and additional GTLP value-added features are discussed.
PAGE 707
SCEA017 List of Figures 1 2 3 4 5 6 7 8 9 Open-Collector Bus System Using BTL/FB+ Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open-Drain Bus System Using GTL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Backplane Physical Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BTL and GTLP Signal-Level Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 708
SCEA017 Background FB+ devices are 5-V VCC BiCMOS translators that operate between TTL logic levels on the card and BTL signal levels on the backplane. The backplane signals are generated by an open collector and a termination network (see Figure 1). The saturation voltage of the pulldown transistor and the forward voltage of the serially connected diode generate the output low-level voltage of 1.1 V. The high level of 2.
PAGE 709
SCEA017 The GTLP family combines the high-drive benefits of the BTL family, with the reduced power consumption of the GTL family. GTLP specifically is designed and optimized for heavily loaded multipoint backplane applications with a slow, controlled, backplane edge rate, and includes features needed for live insertion and withdrawal.
PAGE 710
SCEA017 FB+ and GTLP Characteristics Comparison Table 1 compares the FB2033A with the high-drive GTLP2033 device, which is soon to be released. Each characteristic is discussed in general and then in detail if the difference is material to the use of GTLP devices in BTL/FB+ applications. Values of Cio, ICC, and tpd are design goals and are subject to change. Table 1.
PAGE 711
SCEA017 A-Port/Daughter-Card Side of the Device • Logic levels – The logic levels are compatible because the threshold, VIH, VOH, and VIL logic levels are the same. GTLP is 5-V tolerant. • Transistor types and drive levels – They are not significantly different. Most applications do not require the higher drive and work well with the balanced drive of ±24 mA.
PAGE 712
SCEA017 • Differential input – FB+ devices have a fixed differential input set at 1.55 V, whereas GTLP devices have a variable differential input that is set via the external VREF control pin. Normally, VREF is two-thirds of VTT so that, when VTT is 1.5 V, VREF is 1.0 V. As shown in Figure 5, the GTLP reference level is set by this simple R/2R resistor network, with R typically being a one-fourth-watt resistor in the range of 1 kΩ ± 1%.
PAGE 713
SCEA017 Device Characteristics 7–288 • VCC – FB+ uses 5-V VCC, whereas GTLP uses 3.3-V VCC. The lower VCC is more compatible with newer, higher-performance devices being used in current and future board designs. • Technology – FB+ uses an older 0.8-m bipolar process, whereas GTLP uses a newer 0.65-m CMOS process that has the main advantage of lower power consumption. • ICC – ICC is the amount of current used by the device and is a factor in computing power consumption.
PAGE 714
SCEA017 Table 2.
PAGE 715
SCEA017 • ESD – Both FB+ and GTLP meet the minimum electrostatic discharge (ESD) standards in human-body model (HBM), 2000 V; machine model (MM), 200 V; and charged-device model (CDM), 1000 V. During testing, the GTLP devices pass 4000-V HBM and 3000-V CDM. • Temperature ranges – FB+ is offered in commercial (0°C to 70°C) and military (–55°C to 125°C) temperature ranges, with some of the newer devices also ac specified for the industrial (–40°C to 85°C) temperature range.
PAGE 716
SCEA017 GTLP Data-Sheet Changes Required for BTL/FB+ Applications Analysis of high-drive GTLP TI-SPICE model data of GTLP and BTL signal levels shows little change in dc specifications, timing requirements, and switching characteristics. This is because the GTLP device always is operated from 3.3-V VCC, even if the B-port output voltage is pulled to 2.1 V. Overall voltage swing is about 0.6 V larger than normal GTLP voltage swings when operated at BTL signal levels.
PAGE 717
SCEA017 As shown in Figure 7, the high-drive SN74GTLPH1655DGGR is used on the driver and receiver cards. There is a removable termination card at either end of the backplane to allow performance with different values of RTT to be examined. Two cards (driver and receiver) were modified to operate at BTL signal levels by changing the R/2R VREF resistor network to R/3R. VTT for the entire backplane was changed from 1.5 V to 2.1 V by changing the resistor in the 1.
PAGE 718
SCEA017 10 ns 1.5 V VTT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VTT 0.48 V/ns 0.28 V/ns RTT = 25 Ω RTT = 33 Ω VREF 43.5 MHz RTT = 38 Ω Duty Cycle 45–55% 10 ns VTT RTT = 33 Ω RTT = 50 Ω 0.33 V/ns 0.45 V/ns RTT = 25 Ω VREF 25 MHz RTT = 38 Ω R = 50 Ω TT Duty Cycle 46–54% RTT = 25 Ω 1.5 V 0.5 V/ns RTT = 33 Ω VTT 0.33 V/ns RTT = 38 Ω VREF RTT = 50 Ω 25 ns 11.5 MHz VOL = 0.30 V at 25 Ω VOL = 0.25 V at 33 Ω VOL = 0.20 V at 38 Ω VOL = 0.
PAGE 719
SCEA017 Table 5 compares slew rates and duty cycles for Figures 8 and 9. The slew rates and duty cycles were measured at the optimum termination, which is 33 Ω. Table 5. Waveform Slew Rate and Duty Cycle LEVEL MONITOR POINT DATA FREQUENCY (MHz) L-H SLEW RATE (V/ns) H-L SLEW RATE (V/ns) DUTY CYCLE (%) GTLP G1 B1 GTLP G1 B1 11.5 0.5 0.33 48–52 25 0.45 0.33 GTLP 46–54 G1 B1 43.5 0.48 0.28 45–55 BTL G1 B1 11.5 0.46 0.40 46–54 BTL G1 B1 25 0.52 0.47 46–54 BTL G1 B1 43.5 0.
PAGE 720
SCEA017 There are different levels of recommended IOL for the GTLP device at 0.4 V and 0.55 V, because these are points on the voltage vs current (VI) curve that approximate best where the device will be operated. The absolute IOL limit is twice the recommended limit.
PAGE 721
SCEA017 Glossary BiCMOS Device technology that combines high drive of bipolar outputs with lower power consumption of CMOS inputs Bipolar Device technology that has high drive outputs, but has high power consumption BTL Backplane transistor logic, which operates at signal levels of VTT = 2.1 V, VREF = 1.55 V, and VOL = 1.1 V CMOS Device technology that has balanced drive outputs and low power consumption FB+ FutureBus Plus devices are designed to operate at BTL signal levels.
PAGE 722
SCEA017 References 1. Texas Instruments, Comparing Bus Solutions, application report, March 2000, literature number, SLLA067. 2. Texas Instruments, Fast GTL Backplanes With the GTL1655, application report, February 1999, literature number SCBA015. 3. Texas Instruments, GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic, application report, March 1997, literature number SCEA003A. 4. Texas Instruments, GTLP EVM Overview, presentation, June 2000. 5.
PAGE 723
GTLP Evaluation Module (EVM) User’s Guide SCEA023 June 2001 7–299
PAGE 724
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
PAGE 725
Preface Read This First About This Manual Use this manual to set up and use the GTLP evaluation module (EVM) for the SN74GTLPH1655 and other GTLP devices.
PAGE 726
Information About Cautions and Warnings Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment. This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you. The information in a caution or a warning is provided for your protection.
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–309 1.1 GTLP EVM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–310 1.2 GTLP EVM Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–311 1.3 GTLP EVM Kit Availability . . . . . . . . . . . . . . . . . . . .
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Contents 4 Waveform Measurement and Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–355 4.1 Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Driver Card (D1) Latch Clock (Ch2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–356 4.2 Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Driver Card (D1) Group 1 GTLP Data Out (Ch2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–357 4.
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Figures Figures 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 2–10 2–11 2–12 2–13 2–14 2–15 2–16 2–17 2–18 2–19 2–20 2–21 2–22 2–23 2–24 2–25 2–26 2–27 2–28 2–29 2–30 2–31 2–32 GTLP EVM Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–314 GTLP EVM Top Tray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–315 GTLP EVM Backplane Board . . . . . . . . . . . . . . . . . . . . . .
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Figures 3–1 3–2 3–3 3–4 3–5 3–6 3–7 3–8 4–1 4–2 4–3 4–4 4–5 4–6 4–7 5–1 5–2 5–3 A–1 A–2 A–3 A–4 A–5 A–6 A–7 A–8 A–9 A–10 A–11 A–12 A–13 7–306 Tektronix O-Scope Front (Left) and Top (Right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–350 O-Scope Probe Monitor-Point Adapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–350 Simple Test-Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Tables Tables 2–1 2–2 2–3 2–4 2–5 2–6 2–7 GTLP EVM Group Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–317 GTLP EVM Backplane Eight-Layer Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–318 GTLP EVM Group 1, Bits 1 Through 8 Trace Impedance . . . . . . . . . . . . . . . . . . . . . . . . . 7–319 Termination-Card Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 1 Introduction The Texas Instruments (TI) GTLP evaluation module (EVM) board is used to evaluate the SN74GTLPH1655 in multipoint data-transmission applications in a heavily loaded backplane. The GTLP EVM is a 17.9-in., 20-slot, 0.94-in.-pitch, 8-layer PC backplane board that provides a total of 48 parallel data lines divided into 6 groups of 8 bits staggered into various lengths. The EVM also includes a 1-bit clock along the length of the backplane showing source-synchronous transfer mode.
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GTLP EVM Overview 1.1 GTLP EVM Overview The EVM can be used to evaluate device parameters, while acting as a guide for high-speed board layout. Because GTLP operates over a wide range of frequencies, designers must optimize their designs for the frequency of interest. Additionally, designers can use buried transmission lines and provide additional noise attenuation and EMI suppression to optimize their end product. The board layout is designed and optimized to support high-speed operation up to 100 MHz.
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GTLP EVM Kit Contents 1.2 GTLP EVM Kit Contents This EVM kit comprises the following major parts, components of which are listed in Appendix A.
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GTLP EVM Kit Availability 1.3 GTLP EVM Kit Availability The GTLP EVM kit is not available for resale, but can be obtained and used for short periods of time by contacting the GTLP team at GTLP@list.ti.com. There are six locations worldwide where GTLP EVMs can be obtained: Europe, China, Korea, Japan, and the Americas (2).
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Chapter 2 GTLP EVM Board Typical Test and Setup Configuration This chapter describes the GTLP EVM setup and the configurations used to evaluate the SN74GTLPH1655 transceiver. These configurations can be used to evaluate different transceivers that will be available in the future. Topic Page 2.1 GTLP EVM Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–314 2.2 Top Tray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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GTLP EVM Case 2.1 GTLP EVM Case The EVM is stored and transported in a sturdy plastic case with rollers and extensible handle (see Figure 2–1). The handle locks in position and can be extended or retracted by pressing the release on the underside of the handle. Figure 2–1. GTLP EVM Case The case is suitable for air transportation and has the combination lock set at 394. To lock the case, rotate one or more of the dials from the opening combination.
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Top Tray 2.2 Top Tray The top tray fits snuggly in the GTLP EVM case (see Figure 2–2) and holds the backplane board, power supply, extra clock crystals, and extra termination cards in place. The tray is electrostatic protective foam that holds the backplane board during demonstrations. Figure 2–2.
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Backplane Board 2.3 Backplane Board The backplane board (see Figure 2–3) is typical of backplanes used in commercial applications, and consists of 20 slots with 0.94-in. pitch and 48 data bits, and 1 clock bit on stripline transmission lines. Figure 2–3. GTLP EVM Backplane Board This backplane board is constructed uniquely of six groups of eight data bits each to study the effect of different backplane lengths and driver/receiver placements.
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Backplane Board Figure 2–4. GTLP EVM Backplane Block Diagram X Slot 20 Slot 19 Slot 18 É Slot 17 Slot 16 Slot 15 Slot 14 É Slot 13 Slot 12 Slot 11 Slot 10 Slot 9 É Slot 8 Slot 7 Slot 5 Slot 4 Slot 3 Slot 2 Slot 1 É É É ÉÉ É É ÉÉ É É Slot 6 Backplane Overview X É É Clock Generator X = Termination Card on Back of Connector Table 2–1.
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Backplane Board A logic selection line (MODESEL) connects P1-1 through P1-20. The driver card uses this line to select between source-synchronous and system-clock operation. The demonstration board is an eight-layer board with separate VCC and ground planes. The backplane board stackup is shown in Table 2–2. Embedded microstrip nominal line width is 0.006 in., dielectric material is Nelco N4000-13 with a dielectric constant (50% resin contents) of 3.80 @ 100 MHz. Table 2–2.
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Backplane Board Targeted, nominal, unloaded line impedance was 50 Ω, but, based on post-manufacturing testing, was not consistent. Results for Group 1, bits 1 through 8 are shown in Table 2–3. The backplane natural trace impedance (Zo) is calculated and is a best estimate. The backplane trace impedance with only the connector pins attached (i.e., all cards removed) (Zo′) and the backplane trace impedance in a fully loaded backplane (i.e., 20 cards inserted) (Zo′′) are measured. Table 2–3.
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Connectors 2.4 Connectors An AMP Z-PACK 2-mm, 110-pin, hard-metric (HM) male connector is used in slots 1 through 20 (see Figure 2–5) . Figure 2–5. AMP Z-PACK 2-mm, 110-Pin, Hard-Metric (HM) Male Connector Five pins are used on the backplane, with three different lengths on the backplane daughter-card side. Pins A, B, and C are used for data/VCC, BIAS VCC, and GND, respectively. C-length pins are in the center, and A-length pins are in two rows on either side.
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Connectors Figure 2–6. AMP Pin Lengths * X, U, V are used only for cross-connect applications. Not all versions are tooled.
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Connectors Figure 2–7.
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Power Supply 2.5 Power Supply The power supply (see Figure 2–8) is a universal power supply that accepts 100 V to 240 V, 50/60-Hz ac and uses any wall plug that connects to the IEC 320 two-connector universal socket with the US/Canada Edison plug. An alternate supply cord with a different wall plug must be procured locally, if required. The power-supply output is 24-Vdc at 2.1 A, which is fed to the backplane board using the 5.5-mm plug to J5 (see Figure 2–8), and connects through a 2.
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Power Supply The 3.3 V is further reduced to 1.5 V, 7.5 A by the LT1083CP linear regulator (see Figure 2–9) for the termination voltage (VTT). VTT is set by the combination of R1 and R2 and can be varied in the factory between 0.8 V to 1.8 V, but is set at 1.0 V for field use at GTLP levels. The 5-V power supply is required for driver cards that use both 5-V and 3.3-V VCC, such as the SN74GTLPH16612. There is an option to change the 5-V power supply to 2.5 V for future devices at that voltage node.
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Power Supply Figure 2–10.
PAGE 749
Clock Crystals 2.6 Clock Crystals Clock frequency is controlled by the clock-driver card and is limited by clock-control components to 100 MHz. The GTLP receiver device is used in a latched mode of operation, so GTLP data frequency is equal to one-half the clock frequency. Clock crystals and spares, in frequencies of 66 MHz, 75 MHz, 87 MHz, and 100 MHz, are included with the kit. One crystal can be installed on each clock card, with the others stored in the clock-crystal tube (see Figure 2–11).
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Termination Cards 2.7 Termination Cards Because proper backplane termination has a large effect on signal integrity and is investigated easily, Group 1 has removable termination cards on the back of the backplane (see Figure 2–13). The termination cards are identical, except for the resistor values that are 25 Ω, 33 Ω, 38 Ω, or 50 Ω. One bypass capacitor is mounted with every other termination resistor to limit voltage fluctuations.
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Termination Cards Table 2–4. Termination-Card Stackup Trace Name Use Layer Copper Weight (oz) Top Data signal 1 0.5 VCC plane Ground plane Bottom VCC plane Ground plane Data signal 2 3 4 Physical Representation Dielectric Height (in.) Dielectric Name 0.004 B stage 0.004 Core 0.004 B stage 1 1 0.5 Groups 2 through 6 have 25-Ω fixed termination resistors due to space limitations, and have one bypass capacitor for every four termination resistors.
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Bottom Compartment 2.8 Bottom Compartment The portable oscilloscope and backplane daughter cards are stored under the top tray of the GTLP EVM case (see Figure 2–15). Figure 2–15. Oscilloscope and Backplane Daughter-Card Storage Area Clock Cards Monitored Receiver Cards Unmonitored Receiver Cards Empty Slots Oscilloscope Storage Driver Cards There are 2 clock cards, 19 unmonitored receiver cards, 3 monitored receiver cards, and 2 driver cards in every GTLP EVM kit.
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Measurement Equipment 2.9 Measurement Equipment The Tektronix THS730A Oscilloscope/DMM (O-Scope) (see Figure 2–16) can be stored in the bottom of the case (see Figure 2–15). It is easy to operate and is portable. The O-Scope can monitor two channels simultaneously. Store the O-Scope face down to prevent damage to the buttons during transit. The probes can be stored on top of the O-Scope, as shown, or alongside, depending on the amount of space in either location.
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Clock Cards 2.10 Clock Cards Two clock cards (see Figure 2–17) are included with the EVM, one primary and one spare. The clock cards generate the clock signal that is sent to every slot via mitered lines, so that the clock arrives at exactly the same time at each card. The clock card uses a plug-in half-can oscillator for a reference to two CDC2586 phase-locked-loop clock drivers. These two drivers provide the 20 system clocks used on the backplane. The CDC2586 supports a maximum frequency of 100 MHz.
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Clock Cards Table 2–5. Clock-Card Stackup Trace Name Use Layer Copper Weight (oz) Top Data signal 1 0.5 VCC plane Ground plane Bottom 7–332 VCC plane Ground plane Data signal 2 3 4 Physical Representation Dielectric Height (in.) Dielectric Name 0.004 B stage 0.004 Core 0.004 B stage 1 1 0.
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Driver Cards 2.11 Driver Cards Separate driver and receiver daughter cards were manufactured for use on the backplane because, even though the bidirectional SN74GTLPH1655 device is used, each type of card is hardwired to operate in a certain direction. The driver card generates a data pattern from the system clock and drives the GTLP lines on the backplane. The GTLP devices are hardwired for clocked storage in the A-to-B direction. Data is transmitted on the rising edge of the system clock.
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Driver Cards The driver daughter card (see Figure 2–18) has SMB monitor points for selected LVTTL and GTLP signals, in addition to jumpers for Group 1, bit 1 switching (JB1), system or SN74GTLP1394 source-synchronous clock selection (JB2), and selection of the SN74GTLPH1655 slow or fast edge rate (JB3). The monitor points along the top edge are the latch clock and the master data pattern sent to all SN74GTLPH1655 LVTTL A-port inputs.
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Driver Cards 2.11.1 Single-Bit Selection JB1 three-position jumper is used to set Group 1, bit 1 to pass the normal data pattern, set the signal low, or set the signal high (see Figure 2–19). The JB1 jumper is stored on the lowest pin (see Figure 2–19) when set high, to prevent losing it. The following options are available: - JB1 1-2 shorted - JB1 2-3 shorted - JB1 open Group 1, bit 1 normal data pattern Group 1, bit 1 held low Group 1, bit 1 held high Figure 2–19.
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Driver Cards 2.11.2 Edge-Rate Control The device used as the backplane driver, SN74GTLPH1655, has a feature by which the backplane slew rate is adjustable via an external edge-rate-control (ERC) pin held at 3.3 V (slow) or GND (fast). The ERC is set by the JB3 jumper located below the bit-selection jumper and has two positions: not connected is slow, and shorted is fast (see Figure 2–20). The following ERC options are available: - JB3 open - JB3 shorted Slow edge rate Fast edge rate Figure 2–20.
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Driver Cards 2.11.3 Source-Synchronous Clock/System-Clock Selection Backplanes usually have a system-wide synchronous clock. A system clock provides an absolute reference time signal from the clock card to every daughter card at exactly the same time. Source-synchronous clock operation is different because it allows the absolute system clock to be sent by the backplane driver along with the data. In the EVM, this is implemented with the SN74GTLP1394 transceiver on all daughter cards.
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Receiver Cards 2.12 Receiver Cards Receiver cards place a load on the backplane and provide a point to monitor the signals. There are two types of receiver cards: one that has built-in monitor points, and one with no monitor points. Either type can be placed in any slot in the backplane, typically with the monitored receiver card placed in the slots under observation. There is a monitor point for only one bit per group.
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Receiver Cards Figure 2–22 shows a monitored receiver card. Monitor points on the right side are for GTLP Groups 1, 2, 3, 4, 5, and 6. Monitor points on the top are for LVTTL latch clock, Groups 6, 5, 4, 3, 2, and 1. The LVTTL latch-clock source is either the system clock or source-synchronous clock.
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Receiver Cards Figure 2–22. GTLP EVM Monitored Receiver Card TP13 TP12 TP11 TP10 TP9 TP8 TP7 TP1 TP2 TP3 TP4 TP5 TP6 Note: SN74GTL1655 devices were used on the receiver cards. The SN74GTLPH1655 was in development and initial preproduction samples were used for the driver cards, but insufficient quantities were available for the receiver cards. The SN74GTL1655 and SN74GTLPH1655 are identical, except for the B-port output edge rate (slew) and B-port Cio.
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Backplane Setup 2.13 Backplane Setup 2.13.1 Insertion of Clock Cards The clock-card connectors (see Figure 2–23) use AMP 55-pin, 2-mm, HM connectors and are identical to the backplane termination-card connectors. They can be mated improperly because they are keyed only on one side, whereas the backplane connectors are keyed in the center and do not allow improper insertion.
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Backplane Setup Figure 2–24. Connector Premate (Left), Mating (Center), and Mated (Right) Key Figure 2–25 (left) shows the clock card properly inserted, with the CDC components and the clock crystal facing away from the backplane connectors and daughter cards. Yellow dots are located on the connector and the card to help ensure proper orientation. Figure 2–25 (right) shows the card improperly inserted. Figure 2–25.
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Backplane Setup 2.13.2 Insertion of Clock Crystals Clock crystals are live insertable, unlike the clock card, which is not live insertable. Clock crystals are inserted easily on the clock card by pulling off one crystal and inserting the new crystal (see Figure 2–26). The leads can be bent gently to ease insertion. The clock crystal need not be inserted fully flush with the card for proper operation.
PAGE 767
Backplane Setup 2.13.3 Insertion of Termination Cards Termination-card, AMP Z-PACK, 2-mm, 55-pin, HM male and female connectors are identical to the clock-card connectors, and are inserted directly onto the K and T pins used for slots 1 and 20, VCC, and data bits. Although the termination card connectors are keyed on the top (see Figure 2–27), they can be inserted backward because they are keyed on only one side. Figure 2–27.
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Backplane Setup 2.13.4 Insertion of Driver and Receiver Cards The driver and receiver cards are live insertable and are easy to insert and remove, although some slight side-to-side rocking action might be required. The cards can be inserted into any slot in any order, but only one driver card should be used at any one time. There is no bus contention damage if multiple driver cards are in operation at the same time, this is one key benefit from using the GTLP open-drain technology.
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Backplane Setup Figure 2–30. Close-up View of Connector Keying Wide Key Narrow Key The card should be placed squarely on the connector and pressed down (see Figure 2–31), with very little side-to-side motion. The components are facing left towards slot 1, the power supplies are on the top/right, and the Group 1–6 markings are on the bottom/left. The card in Figure 2–31 is being inserted into slot 20. Figure 2–31.
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Backplane Setup Figure 2–32.
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Chapter 3 Oscilloscope Operation Topic Page 3.1 Oscilloscope Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–350 3.2 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Oscilloscope Setup 3.1 Oscilloscope Setup The recommended oscilloscope (O-Scope) for the GTLP EVM is the Tektronix THS730A (see Figure 3–1). It allows only two-channel operation, which should be sufficient for most investigations done with the demonstration backplane. Figure 3–1. Tektronix O-Scope Front (Left) and Top (Right) SMB adapters (see Figure 3–2) are needed to properly mate Tektronix probes with the test points.
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Measurements 3.2 Measurements The first step in taking measurements is to plug one probe into channel 1 (CH 1) of the O-Scope and connect the opposite end to the desired monitor point. Plug the other probe into channel 2 (CH 2) of the O-Scope and connect the opposite end to the desired monitor point (see Figures 3–1 and 3–3). Chapter 4, Waveform Measurement and Interpretation, discusses which monitor points should be used and why. Figure 3–3.
PAGE 774
Measurements Waveforms similar to those in Figure 3–5, depending on how the O-Scope presets were set, are displayed. In Figure 3–5, CH 2 is selected. Figure 3–5.
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Measurements To adjust the timing (x or horizontal axis), press the appropriate side of the SEC/DIV button (see Figure 3–6). An example of the results is shown for 50 ns/division and 100 ns/division. Timing is the same for both channels and is independent of channel selection. Figure 3–6. Timing Adjustment To adjust the voltage (y or vertical axis), press the top or bottom of the VOLTS/DIV button (see Figure 3–7). An example of the results is shown for Ch2 at 1 V (center) and Ch2 at 2 V (right).
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Measurements To adjust the trigger, press the MENU button (see Figure 3–8), then press Trigger Source to display a submenu. In the submenu, select Ch1, Ch2, or Ext [DMM] by repeatedly pressing the same Trigger Source button. After the appropriate trigger is selected, press the CLEAR MENU button to restore the O-Scope to operation. Figure 3–8.
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Chapter 4 Waveform Measurement and Interpretation In this chapter, five different measurement cases are discussed in detail, and several more measurement combinations are outlined. Many other combinations are possible. Topic Page 4.1 Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Driver Card (D1) Latch Clock (Ch2) . . . . . . . . . . . . . . . . . . . . . . . . . . 7–356 4.2 Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Driver Card (D1) Group 1 GTLP Data Out (Ch2) . .
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Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Driver Card (D1) Latch Clock (Ch2) 4.1 Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Driver Card (D1) Latch Clock (Ch2) Figure 4–1 shows the probe hookup and related O-Scope output for Case 1. The LVTTL latch clock signal goes to the SN74GTLPH1655 driving device CLK pin, and the LVTTL data signal goes to the A-port input pin, specifically the Group 1, bit 1 data signal. Figure 4–1.
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Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Driver Card (D1) Group 1 GTLP Data Out (Ch2) 4.2 Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Driver Card (D1) Group 1 GTLP Data Out (Ch2) Figure 4–2 shows the probe hookup and O-Scope output for Case 2. The LVTTL data goes into the SN74GTLPH1655 driving device A-port input, and the GTLP data comes out of the B-port output.
PAGE 780
Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Receiver Card (R2) Group 1 GTLP Data In (Ch2) 4.3 Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Receiver Card (R2) Group 1 GTLP Data In (Ch2) Figure 4–3 shows the probe hookup and O-Scope output for Case 3. The LVTTL data input goes to the SN74GTLPH1655 driving device A-port input, and the GTLP data input goes to the SN74GTL1655 receiving device B-port in slot 2.
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Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Receiver Card (R2) Group 1 LVTTL Data Out (Ch2) 4.4 Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Receiver Card (R2) Group 1 LVTTL Data Out (Ch2) Figure 4–4 shows the probe hookup and O-Scope output for Case 4. The LVTTL data input goes to the SN74GTLPH1655 driving device A-port input, and the LVTTL data output of the SN74GTL1655 receiving device goes to A port in slot 2.
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Timing Relationship of Receiver Card (R2) Group 1 GTLP Data In (Ch1) 4.5 Timing Relationship of Receiver Card (R2) Group 1 GTLP Data In (Ch1) and Receiver Card (R20) Group 1 GTLP Data In (Ch2) Figure 4–5 shows the probe hookup and O-Scope output for Case 5. You can see the flight-time delay between the output of the SN74GTLPH1655 driving device B port in slot 1 and the SN74GTL1655 receiving device B port in slot 20. Total flight time is about 9 ns. Figure 4–5.
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Monitored Waveforms 4.6 Monitored Waveforms There are differences in waveforms between GTLP monitor test points and measurements taken at the backplane connector pins, due to interference from LVTTL data and clock signals not shielded adequately on the daughter cards. This concern is only for this demonstration backplane because there is no reason to extend the GTLP signals past the GTLP device B-port output pins on operational daughter cards.
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Chapter 5 Troubleshooting Topic Page 5.1 Spare Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–364 5.2 Replacing 5-A Fuse F2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–365 5.3 Replacing 2.5-A Fuse F1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–366 5.4 Damage to the Daughter Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Spare Parts 5.1 Spare Parts Each EVM is equipped with spare fuses and jumpers (see Figure 5–1). Figure 5–1.
PAGE 786
Replacing 5-A Fuse F2 5.2 Replacing 5-A Fuse F2 Fuse F2 (see Figure 5–2) provides power from the 3.3-V switching regulator to the 3.3-V power plane and blows if VCC is shorted to GND. Shorting can occur if a connector pin is bent during insertion or if measurements are taken directly from the backplane. F2 can be replaced easily with one of the spare fuses. Simply disconnect power from the board, and pull out the fuse with pliers (see Figure 5–2). Push in the new fuse, and reconnect the power supply.
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Replacing 2.5-A Fuse F1 5.3 Replacing 2.5-A Fuse F1 Fuse F1 (see Figure 5–3) provides power from the power supply to the 3.3-V and 5-V switching regulators and blows if the switching regulators fail. It is replaced as easily as fuse F2. Disconnect the power from the board, pull out the fuse with pliers, push in the new fuse, then reconnect the power supply. Figure 5–3.
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Damage to the Daughter Cards 5.4 Damage to the Daughter Cards The daughter cards are not field repairable and must be returned to the factory for repair.
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Appendix AppendixAA Bill of Materials, Schematics, Board Layouts, and Suggested Specifications Topic Page A.1 GTLP EVM Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–370 A.2 Board Layouts and Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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GTLP EVM Bill of Materials A.1 GTLP EVM Bill of Materials - Backplane Device Type 7–370 Quantity Z-PAK 110-Pin Male Connector 20 Z-PAK 55-Pin Male Connector 1 2.5 AMP Fuseholder 1 5 AMP Fuseholder 1 Surface Mount 0.01uF Cap 3 Surface Mount 0.1uF Cap 75 Surface Mount Tantalum 10uF/10V Cap 4 Surface Mount Tantalum 1uF/35V Cap 2 Surface Mount Tantalum 47uF/10V Cap 2 Surface Mount 100 ohm Resistor 1 Surface Mount 120 ohm Resistor 1 Surface Mount 1.
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GTLP EVM Bill of Materials - Clock Driver Card Device Type Quantity Z-PAK 55-Pin Female Connector 1 CDC2586 TQFP Clock Driver 2 Surface Mount 0.1uF Cap 10 Surface Mount 453 ohm Resistor 1 Oscillator Mount 1 SMB Coax Connector 1 - Termination Card Device Type Quantity Z-PAK 55-Pin Female Connector 1 Surface Mount 0.
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GTLP EVM Bill of Materials - Monitored Driver Card Device Type Quantity Z-PAK 55-Pin Female Connector 1 SN74ALVC126 TVSOP Buffer 1 SN74GTLP1394 TVSOP Transceiver 1 SN74GTLPH1655 TSSOP UBT 3 SN74ALVCH16344 TSSOP Buffer 2 CDC351 Clock Buffer 1 SN74LVC112A JK Flip-Flop 3 SN74LVC04 Inverter 1 Surface Mount 0.
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Board Layouts and Schematics A.2 Board Layouts and Schematics Figure A–1. Backplane Layout, Front Side P1–20 Group 1 R6 R5 P1–19 Ç ÇÇ Ç ÇÇ P1–18 LED 2 LED 1 U2 P1–17 LED 3 P1–16 JP1 Group 2 P1–13 F1 P1–14 5 Volts @ 1 Amp. P1–15 P3 P1–11 J5 P1–12 3.3 Volts @ 7.5 Amps. P1–10 P1–8 Group 4 P1–7 P1–6 F2 P1–5 U1 Group 5 P1–4 P1–3 Group 6 U2, R5, and R6 are not installed at this time.
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Board Layouts and Schematics Figure A–2.
PAGE 795
Board Layouts and Schematics Figure A–3. Driver-Card and Receiver-Card Connector Pinout P1-X P1-1B and P1-20B A B C D E GND GND 5V 5V 1 2 Sys. Clk. 3.3V 3.3V GND 3.3V 3.3V 2 3.3V GND 3.3V 3.3V 3 G1D3 G1D1 GND G1D4 G1D2 3 G1D3 G1D1 GND G1D4 G1D2 4 G1D7 1.5V G1D5 1.5V GND G1D6 1.5V 5 G1D7 1.5V G1D5 1.5V GND GND G1D8 1.5V 4 5 G1D8 1.5V G1D6 1.
PAGE 796
Board Layouts and Schematics Figure A–4.
PAGE 797
C21 R11 C19 TP8 TP7 LVC112A LVC112A LVC112A CLK DATA U9 U8 U7 ALVC04 3.
PAGE 798
Board Layouts and Schematics Figure A–6.
PAGE 799
C13 GTLP1394 U4 C14 ALVCH126 U5 RTerm C9 U3 GTL 1655 C12 RTerm RTerm OUTPUT Connector J1–x AMP type A 100623–1 C11 U2 GTL 1655 C10 RTerm RECEIVER CARD (Standard) C8 RTerm C18 C16 C15 U1 GTL 1655 RTerm column 1 3 inches 3.5 inches C17 R1 C1 R2 .76 inch Board Layouts and Schematics Figure A–7.
PAGE 800
TP12 CLK TP11 TP10 TP9 TP8 GP5 GP4 GP3 GP2 GP1 SMB SMB SMB SMB SMB GP6 SMB SMB TP7 SMB SMB RECEIVER CARD (Monitor) SMB 3 inches 10K network 10K network RTerm RTerm 10K network 10K network RTerm RTerm 10K network C7 R14 C6 R13 U3 GTL 1655 C5 C10 R12 C8 C3 R10 C2 R9 SMB ALVCH126 GTLP1394 U5 R15 U4 R7 R6 C11 R5 R4 R8 AMP type A 100623–1 J1–x R3 C15 C18 column 1 C9 C13 TP3 GP3 TP4 GP4 TP5 GP5 U1 GTL 1655 U2 GTL 1655 SMB C14 TP2 GP2 RTerm RTerm C4 R11
PAGE 801
Board Layouts and Schematics Figure A–9.
PAGE 802
TP1 CLOCK CARD R1 C6 C2 C3 U2 CLOCK DRIVER C5 U3 C7 C9 CLOCK DRIVER C4 C8 C10 AMP type C 100161–1 J3 column 1 2.5 inches CLOCK U1 SMB Monitor OUTPUT Connector .76 inch Board Layouts and Schematics C1 Figure A–10. Clock-Card Layout 7–382 2.
PAGE 803
Clock Card 51.1 3.3V 1 2 3 4 5 R1 TP1 Sheet Vcc 1 GND 4 N/C 3.3V .1uF .1uF C6 CLK_OUT10 CLK_OUT9 CLK_OUT8 CLK_OUT7 26 25 24 23 22 21 20 19 18 17 16 15 14 C7 Vcc 4Y3 GND Vcc 4Y2 GND Vcc 4Y1 GND GND Vcc 3Y3 GND 39 38 37 36 35 34 33 32 31 30 29 28 27 (C) J3 7–383 Board Layouts and Schematics CLK_OUT13 CLK_OUT14 CLK_OUT15 CLK_OUT16 CLK_OUT17 CLK_OUT18 CLK_OUT19 CLK_OUT20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E2 E3 E4 E5 E6 E7 .
PAGE 804
R5 C4 C2 R2 R4 C3 R1 R3 C1 R6 R8 AMP type C 100161–1 J4 Output Connector R7 column 1 1.5 inch Standard termination card Board Layouts and Schematics Figure A–12.
PAGE 805
Figure A–13. Standard-Termination-Card Schematic C3 C4 1.
PAGE 806
General Information GTL GTLP ETL BTL/FB+ VME Application Reports Mechanical Data 8–1
PAGE 807
Contents Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D (R-PDSO-G**) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGG (R-PDSO-G**) . . . . . . . . . . . . . . . . . .
PAGE 808
ORDERING INSTRUCTIONS Electrical characteristics presented in this data book, unless otherwise noted, apply for the circuit type(s) listed in the page heading regardless of package. The availability of a circuit function in a particular package is denoted by an alphabetical reference above the pin-connection diagram(s). These alphabetical references refer to mechanical outline drawings shown in this section.
PAGE 809
ORDERING INSTRUCTIONS Table 1. Normal Dimensions of Packing Materials CARRIER-TAPE WIDTH (mm) COVER-TAPE WIDTH (mm) REEL WIDTH (mm) REEL DIAMETER (mm) 8 5.4 9.0 178 12 9.2 12.4 330 16 13.3 16.4 330 24 21.0 24.4 330 32 25.5 32.4 330 44 37.5 44.4 330 56 49.5 56.4 330 All material meets or exceeds industry guidelines for ESD protection. Dimensions are selected based on package size and design configurations.
PAGE 810
ORDERING INSTRUCTIONS Table 2. Selected Tape-and-Reel Specifications PACKAGE D SOIC DW SOT SSOP DBV DCK DB DL DGG TSSOP PW DBB TVSOP DGV NO. OF PINS CARRIER-TAPE WIDTH (mm) POCKET PITCH (mm) QTY/REEL 14 16.00 8.00 2500 16 16.00 8.00 2500 16 16.00 8.00/12.00 1000 20 24.00 12.00 1000 5 8.00 4.00 3000 5 8.00 4.00 3000 14 16.00 12.00 2000 16 16.00 12.00 2000 20 16.00 12.00 2000 24 16.00 12.00 2000 48 32.00 16.00 1000 48 24.00 12.00 2000 56 24.
PAGE 811
MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°–ā8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D.
PAGE 812
MECHANICAL DATA DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°–ā8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. 8–8 All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 813
MECHANICAL DATA DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–ā8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 814
MECHANICAL DATA DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.012 (0,305) 0.008 (0,203) 48 0.005 (0,13) M 25 0.006 (0,15) NOM 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / D 08/97 NOTES: A. B.
PAGE 815
MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.291 (7,39) Gage Plane 0.010 (0,25) 1 8 0°–ā8° A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** 0.004 (0,10) 16 20 24 28 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) 0.
PAGE 816
MECHANICAL DATA GKE (R-PBGA-N96) PLASTIC BALL GRID ARRAY 5,60 5,40 4,00 TYP 0,80 0,40 12,00 TYP 0,40 13,60 13,40 0,80 T R P N M L K J H G F E D C B A 1 2 3 4 5 6 0,95 0,85 1,40 MAX Seating Plane 0,55 0,45 0,45 0,35 0,08 M 0,10 4188953/A 10/98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGA configuration MicroStar BGA is a trademark of Texas Instruments.
PAGE 817
MECHANICAL DATA GKF (R-PBGA-N114) PLASTIC BALL GRID ARRAY 4,00 TYP 5,60 5,40 0,80 0,40 16,10 15,90 0,80 W V U T R P N M L K J H G F E D C B A 14,40 TYP 1 2 3 4 5 6 0,95 0,85 1,40 MAX Seating Plane 0,55 0,45 0,08 M 0,45 0,35 0,10 4188954/A 10/98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGA configuration MicroStar BGA is a trademark of Texas Instruments.
PAGE 818
MECHANICAL DATA PCA (S-PQFP-G100) PLASTIC QUAD FLATPACK (DIE DOWN) 0,27 0,17 0,50 75 0,08 M 51 Heat Slug 76 50 100 26 1 0,13 NOM 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0°–ā7° 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040288 / B 10/96 NOTES: A. B. C. D. 8–14 All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 819
MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°–ā8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 820
MECHANICAL DATA RC (S-PQFP-G52) PLASTIC QUAD FLATPACK 0,38 0,22 0,65 39 0,13 M 27 40 26 52 14 0,16 NOM 1 13 7,80 TYP 10,20 SQ 9,80 13,45 SQ 12,95 Gage Plane 0,25 0,05 MIN 2,20 1,80 0°–ā7° 1,03 0,73 Seating Plane 2,45 MAX 0,10 4040151 / B 03/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
PAGE 821
MECHANICAL DATA WD (R-GDFP-F**) CERAMIC DUAL FLATPACK 48 LEADS SHOWN 0.120 (3,05) 0.075 (1,91) 0.009 (0,23) 0.004 (0,10) 1.130 (28,70) 0.870 (22,10) 0.370 (9,40) 0.250 (6,35) 0.390 (9,91) 0.370 (9,40) 0.370 (9,40) 0.250 (6,35) 1 48 0.025 (0,635) A 0.014 (0,36) 0.008 (0,20) 24 25 NO. OF LEADS** 48 56 A MAX 0.640 (16,26) 0.740 (18,80) A MIN 0.610 (15,49) 0.710 (18,03) 4040176 / D 10/97 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters).