Datasheet

SN74F657
OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER
AND 3-STATE OUTPUTS
SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993
2–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Note 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC
= 5 V,
C
L
= 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
T
A
= 25°C
V
CC
= 4.5 V to 5.5 V,
C
L
= 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
T
A
= MIN to MAX
†
UNIT
MIN TYP MAX MIN MAX
t
PLH
AorB
BorA
2.5 4.2 7.5 2.5 8
ns
t
PHL
A
or
B
B
or
A
3 4 7.5 3 8
ns
t
PLH
A
PARITY
6 8.4 14 6 16
ns
t
PHL
A
PARITY
6.8 8.5 15 6.8 16
ns
t
PLH
ODD/EVEN
PARITY ERR
4 6.4 11 4 12
ns
t
PHL
ODD/EVEN
PARITY
,
ERR
4.5 6.9 11.5 4.5 12.5
ns
t
PLH
B
ERR
8 12.7 20.5 7.5 22.5
ns
t
PHL
B
ERR
8 13.4 20.5 7.5 22.5
ns
t
PLH
PARITY
ERR
6 8.1 15.5 6 16.5
ns
t
PHL
PARITY
ERR
7.5 8.8 15.5 7.5 17
ns
t
PZH
OE
A B PARITY or ERR
‡
3 5.3 8 3 9
ns
t
PZL
OE
A
,
B
,
PARITY
, or
ERR
‡
4 5.4 9.5 4 11
ns
t
PHZ
OE
A B PARITY or ERR
‡
2 4.2 7.5 2 8
ns
t
PLZ
OE
A
,
B
,
PARITY
,
or
ERR
‡
2 3.7 6 2 6.5
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡
These delay times reflect the 3-state recovery time only and not the signal through the buffers or parity check circuitry. To assure valid information
at the ERR
output pin, time must be allowed for the signal to propagate through the drivers (B to A), and to the ERR output. Valid data at the ERR
output is greater than or equal to (B to A) + (A to PARITY).
NOTE 2: Load circuits and waveforms are shown in Section 1.