SN74F657
OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER
AND 3-STATE OUTPUTS
SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
T/R
OE
ERR
A1
A2
A3
A4
A5
A6
A7
A8
DD/EVEN
PARIT
B2
B3
B4
B5
B6
B7
B8
B1
1
24
3
4
2
5
6
8
9
10
11
23
22
21
20
17
16
15
14
13
12
