Datasheet

SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
V
CC
= 5 V,
T
A
= 25°C
MIN MAX UNIT
MIN MAX
f
clock
Clock frequency 0 100 0 90 MHz
CLK high or low (loading) 5 5
t
Pulse duration
CLK (counting)
High 4 4
ns
t
w
Pulse
duration
CLK
(counting)
Low 6 7
ns
CLR low 5 5
Data before CLK↑ High or low 5 5
LOAD before CLK↑
High 11 11.5
t
su
Setup time
LOAD
b
e
f
ore
CLK↑
Low 8.5 9.5
ns
ENP and ENT before CLK↑
High 11 11.5
ENP
and
ENT
before
CLK↑
Low 5 5
Data after CLK↑ High or low 2 2
t
h
Hold time
LOAD after CLK↑
High 2 2
ns
t
h
Hold
time
LOAD
a
ft
er
CLK↑
Low 0 0
ns
ENP and ENT after CLK↑ High or low 0 0
t
su
Inactive-state setup time, CLR high before CLK↑
†
6 6 ns
†
Inactive-state setup time also is referred to as recovery time.
switching characteristics (see Note 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC
= 5 V,
C
L
= 50 PF,
R
L
= 500 Ω,
T
A
= 25°C
V
CC
= 4.5 V TO 5.5 V,
C
L
= 50 PF,
R
L
= 500Ω,
T
A
= MIN TO MAX
‡
UNIT
MIN TYP MAX MIN MAX
f
max
100 120 90 MHz
t
PLH
CLK (LOAD high)
Any Q
2.7 5.1 7.5 2.7 8.5
ns
t
PHL
CLK
(LOAD
hi
g
h)
A
ny
Q
2.7 7.1 10 2.7 11
ns
t
PLH
CLK (LOAD low)
Any Q
3.2 5.6 8.5 3.2 9.5
ns
t
PHL
CLK
(LOAD
l
ow
)
A
ny
Q
3.2 5.6 8.5 3.2 9.5
ns
t
PLH
CLK
RCO
4.2 9.6 14 4.2 15
ns
t
PHL
CLK
RCO
4.2 9.6 14 4.2 15
ns
t
PLH
ENT
RCO
1.7 4.1 7.5 1.7 8.5
ns
t
PHL
ENT
RCO
1.7 4.1 7.5 1.7 8.5
ns
t
PHL
CLR
Any Q
4.7 8.6 12 4.7 13
ns
t
PHL
CLR
RCO
3.7 7.6 10.5 3.7 11.5
ns
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 4: Load circuits and waveforms are shown in Figure 1.