Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver SOIC 14

SN74F125

QUADRUPLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SDFS016B – JANUARY 1989 – REVISED JULY 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-State Outputs Drive Bus Lines or Buffer

Memory Address Registers

description/ordering information

The SN74F125 features independent line drivers

with 3-state outputs. Each output is disabled when

the associated output-enable (OE

) input is high.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – N Tube SN74F125N SN74F125N

SOIC D

Tube SN74F125D

F125

0°C to 70°C

SOIC

–

Tape and reel SN74F125DR

F125

SOP – NS Tape and reel SN74F125NSR 74F125

SSOP – DB Tape and reel SN74F125DBR F125

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

FUNCTION TABLE

(each buffer)

INPUTS

OUTPUT

OE A

L H H

L LL

H X Z

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D, DB, N, OR NS PACKAGE

(TOP VIEW)

1OE

2OE

GND

4OE

3OE

Summary of content (13 pages)

PAGE 1
SN74F125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SDFS016B – JANUARY 1989 – REVISED JULY 2002 D D, DB, N, OR NS PACKAGE (TOP VIEW) 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers 1OE 1A 1Y 2OE 2A 2Y GND description/ordering information The SN74F125 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.
PAGE 2
SN74F125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SDFS016B – JANUARY 1989 – REVISED JULY 2002 logic diagram (positive logic) 1OE 1A 2OE 2A 3OE 3A 4OE 4A 1 2 3 1Y 4 5 6 2Y 10 9 8 3Y 13 12 11 4Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . .
PAGE 3
SN74F125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SDFS016B – JANUARY 1989 – REVISED JULY 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II IIH IIL IOZH IOZL IOS‡ TEST CONDITIONS VCC = 4.5 V, II = – 18 mA IOH = – 3 mA VCC = 4 4.5 5V IOH = – 15 mA IOH = – 3 mA VCC = 4.75 V, VCC = 4.5 V, TYP† MIN 2.4 3.3 2 3.1 0.4 VI = 2.7 V VI = 0.5 V VCC = 5.5 V, VCC = 5.5 V, UNIT – 1.2 V V 2.
PAGE 4
SN74F125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SDFS016B – JANUARY 1989 – REVISED JULY 2002 PARAMETER MEASUREMENT INFORMATION 7V From Output Under Test CL (see Note A) 500 Ω S1 From Output Under Test Test Point CL (see Note A) 500 Ω Open 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 7V Open Collector LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V Timing Input 1.5 V 0V tw tsu 3V 1.5 V Input 1.5 V th 3V 1.5 V 1.
PAGE 5
PACKAGE OPTION ADDENDUM www.ti.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 to Customer on an annual basis.
PAGE 7
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74F125DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74F125NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74F125DR SN74F125NSR SOIC D 14 2500 367.0 367.0 38.0 SO NS 14 2000 367.0 367.0 38.
PAGE 9
PAGE 10
PAGE 11
PAGE 12
PAGE 13
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.