Datasheet

SN74F112
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Note 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC
= 5 V,
C
L
= 50 pF,
R
L
= 500 Ω,
T
A
= 25°C
V
CC
= 4.5 V to 5.5 V,
C
L
= 50 pF,
R
L
= 500Ω,
T
A
= MIN to MAX
†
UNIT
MIN TYP MAX MIN MAX
f
max
110 130 100 MHz
t
PLH
CLK
QorQ
1.2 4.6 6.5 1.2 7.5
ns
t
PHL
CLK
Q
or
Q
1.2 4.6 6.5 1.2 7.5
ns
t
PLH
PRE or CLR
QorQ
1.2 4.1 6.5 1.2 7.5
ns
t
PHL
PRE
or
CLR
Q
or
Q
1.2 4.1 6.5 1.2 7.5
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 3: Load circuits and waveforms are shown in Section 1.