Datasheet

SN74F1056
8-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDFS085A – AUGUST 1992 – REVISED JULY 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Designed to Reduce Reflection Noise
Repetitive Peak Forward Current 300 mA
8-Bit Array Structure Suited for
Bus-Oriented Systems
description
This Schottky barrier diode bus-termination array
is designed to reduce reflection noise on memory
bus lines. This device consists of an 8-bit
high-speed Schottky diode array suitable for a
clamp to GND.
The SN74F1056 is characterized for operation
from 0°C to 70°C.
schematic diagrams
1
2
3
4
7
8
9
10
1
2
3
4
5
6
7
8
6
5
15
14
13
12
11
10
GND
GND
GND
GND
GND
GND
GND
GND
D01
D02
D03
D04
D05
D06
D07
D08
D01
D02
D03
D04
D05
D06
D07
D08
SC Package D Package
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SC PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D01
D02
D03
D04
D05
D06
D07
D08
NC
GND
GND
GND
GND
GND
GND
NC
D PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
D01
D02
D03
D04
GND
GND
D05
D06
D07
D08