Datasheet


    
SCDS038I − DECEMBER 1997 − REVISED OCTOBER 2003
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1A
1OE
SW
1B
2A
2OE
SW
2B
3A
3OE
SW
3B
4A
4OE
SW
4B
2
1
5
4
9
10
12
13
3
6
8
11
Pin numbers shown are for the D, DGV, PW, and RGY packages.
simplified schematic, each FET switch
A
(OE)
B