Datasheet

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SN74CBTD3306

DUAL FET BUS SWITCH

WITH LEVEL SHIFTING

SCDS030L − JANUARY 1996 − REVISED JANUARY 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 5-Ω Switch Connection Between Two Ports

D TTL-Compatible Input Levels

D Designed to Be Used in Level-Shifting

Applications

description/ordering information

The SN74CBTD3306 features two independent

line switches. Each switch is disabled when the

associated output-enable (OE

) input is high. A

diode to V

is integrated on the chip to allow for

level shifting from 5-V signals at the device inputs

to 3.3-V signals at the device outputs.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC D

Tube SN74CBTD3306D

CC306

40°Cto85°C

SOIC − D

Tape and reel SN74CBTD3306DR

CC306

−40°C to 85°C

TSSOP PW

Tube SN74CBTD3306PW

CC306

TSSOP − PW

Tape and reel SN74CBTD3306PWR

CC306

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

FUNCTION TABLE

(each bus switch)

INPUT

FUNCTION

L A port = B port

H Disconnect

logic diagram (positive logic)

2A 2B

2OE

1OE

D OR PW PACKAGE

(TOP VIEW)

2OE

1OE

GND

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (12 pages)

PAGE 1
SN74CBTD3306 DUAL FET BUS SWITCH WITH LEVEL SHIFTING SCDS030L − JANUARY 1996 − REVISED JANUARY 2004 D 5-Ω Switch Connection Between Two Ports D TTL-Compatible Input Levels D Designed to Be Used in Level-Shifting D OR PW PACKAGE (TOP VIEW) 1OE 1A 1B GND Applications description/ordering information 1 8 2 7 3 6 4 5 VCC 2OE 2B 2A The SN74CBTD3306 features two independent line switches. Each switch is disabled when the associated output-enable (OE) input is high.
PAGE 2
SN74CBTD3306 DUAL FET BUS SWITCH WITH LEVEL SHIFTING SCDS030L − JANUARY 1996 − REVISED JANUARY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 3
SN74CBTD3306 DUAL FET BUS SWITCH WITH LEVEL SHIFTING SCDS030L − JANUARY 1996 − REVISED JANUARY 2004 switching characteristics over recommended ranges of supply voltage and operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) † PARAMETER FROM (INPUT) TO (OUTPUT) tpd† A or B B or A ten OE A or B tdis OE A or B MIN MAX UNIT 0.25 ns 2.1 5.4 ns 1 4.
PAGE 4
SN74CBTD3306 DUAL FET BUS SWITCH WITH LEVEL SHIFTING SCDS030L − JANUARY 1996 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE 4 4 3.75 100 μA 3.75 3.5 6 mA 12 mA 3.5 3.25 24 mA 3 2.75 2.5 2.25 2 1.75 1.5 4.5 VOH − Output Voltage High − V VOH − Output Voltage High − V TA = 85°C TA = 25°C 100 μA 6 mA 12 mA 24 mA 3.25 3 2.75 2.5 2.25 2 1.75 4.75 5 5.25 5.5 5.75 1.5 4.5 4.
PAGE 5
PACKAGE OPTION ADDENDUM www.ti.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 7
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74CBTD3306DR Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN74CBTD3306DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN74CBTD3306PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74CBTD3306DR SOIC D 8 2500 340.5 338.1 20.6 SN74CBTD3306DR SOIC D 8 2500 367.0 367.0 35.0 SN74CBTD3306PWR TSSOP PW 8 2000 364.0 364.0 27.0 SN74CBTD3306PWR TSSOP PW 8 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.