Datasheet


      
      
SCDS140 − OCTOBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
A1
B1
A8
OE
B8
BIASV
SW
SW
2
9
48
1
18
11
simplified schematic, each FET switch (SW)
A
EN
†
B
†
EN is the internal enable signal applied to the switch.
Undershoot
Protection Circuit