Datasheet


   
      
SCDS121B − JUNE 2003 − REVISED OCTOBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1B2
1B1
12A
1A
S0
S1
S2
1B3
12B2
12B1
12B3
2
27
1
56
55
54
53
3
30
29
28
SW
SW
SW
SW
SW
SW
simplified schematic, each FET switch (SW)
A
EN
†
B
†
EN is the internal enable signal applied to the switch.
Undershoot
Protection Circuit