Datasheet
1A
1OE
SW
1B
2A
2OE
SW
2B
2
1
5
7
3
6
SN74CB3Q3306A
SCDS113E –DECEMBER 2002–REVISED JANUARY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION/ORDERING INFORMATION
The SN74CB3Q3306A is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of
the pass transistor, providing a low and flat ON-state resistance (r
on
). The low and flat ON-state resistance allows
for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device
also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus.
Specifically designed to support high-bandwidth applications, the SN74CB3Q3306A provides an optimized
interface solution ideally suited for broadband communications, networking, and data-intensive computing
systems.
The SN74CB3Q3306A is organized as two 1-bit switches with separate output-enable (1OE, 2OE) inputs. It can
be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit bus switch is
ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high,
the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry prevents damaging
current backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Table 1. FUNCTION TABLE
(EACH BUS SWITCH)
INPUT INPUT/OUTPUT
FUNCTION
OE A
L B A port = B port
H Z Disconnect
LOGIC DIAGRAM (POSITIVE LOGIC)
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