Datasheet

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1B11A
OE
1B2
SW
SW
2B12A
2B2
SW
SW
3B13A
3B2
SW
SW
4B14A
4B2
SW
SW
S
4
7
9
12
1
15
2
3
5
6
11
10
14
13
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
A
EN
(1)
B
(1) EN is the internal enable signal applied to the switch.
Charge
Pump
V
CC
SN74CB3Q3257
4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS135A – SEPTEMBER 2003 – REVISED MARCH 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
3