Datasheet


   
    
SCDS154B − OCTOBER 2003 − REVISED DECEMBER 2004
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1A1
SW
1B1
1A4
1OE
SW
1B4
2A1
SW
2B1
2A4
2OE
SW
2B4
2
8
1
11
17
19
18
12
9
3
simplified schematic, each FET switch (SW)
A
EN
†
B
†
EN is the internal enable signal applied to the switch.
Charge
Pump
V
CC