Datasheet
SCES622 – JANUARY 2005
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1A1
SW
1B1
1A8
1OE
SW
1B8
3A1
SW
3B1
3A8
3OE
SW
3B8
A5
D6
A4
J5
M6
J4
A2
D1
J2
M1
2A1
SW
2B1
2A8
2OE
SW
2B8
4A1
SW
4B1
4A8
4OE
SW
4B8
E5
H5
H4
N5
T5
T4
E2
H2
N2
T2
simplified schematic, each FET switch (SW)
A
EN
†
B
†
EN is the internal enable signal applied to the switch.
Charge
Pump
V
CC