Datasheet

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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
1A
1OE
SW
1B
3A
3OE
SW
3B
2A
2OE
SW
2B
4A
4OE
SW
4B
2
1
9
10
3
8
5
4
12
13
6
11
Pin numbers shown are for the DGV, PW, and RGY packages.
SN74CB3Q3125
QUADRUPLE FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS143B – OCTOBER 2003 – REVISED MARCH 2005
The SN74CB3Q3125 is organized as four 1-bit bus switches with separate output-enable (1 OE, 2 OE, 3 OE, 4 OE)
inputs. It can be used as four 1-bit bus switches or as one 4-bit bus switch. When OE is low, the associated 1-bit
bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
OE is high, the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B
ports.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry prevents damaging
current backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN – RGY Tape and reel SN74CB3Q3125RGYR BU125
SSOP (QSOP) – DBQ Tape and reel SN74CB3Q3125DBQR BU125
–40°C to 85°C Tube SN74CB3Q3125PW
TSSOP – PW BU125
Tape and reel SN74CB3Q3125PWR
TVSOP – DGV Tape and reel SN74CB3Q3125DGVR BU125
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(EACH BUS SWITCH)
INPUT INPUT/OUTPUT
FUNCTION
OE A
L B A port = B port
H Z Disconnect
LOGIC DIAGRAM (POSITIVE LOGIC)
2