Datasheet

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PARAMETER MEASUREMENT INFORMATION
V
OH
V
OL
C
L
(see Note A)
TEST CIRCUIT
S1
2 × V
CC
Open
GND
R
L
R
L
t
PLH
t
PHL
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
V
CC
0 V
V
OH
V
OL
0 V
V
OL
+ V
∆
V
OH
− V
∆
0 V
Output
Control
(V
IN
)
V
CC
V
CC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (t
pd(s)
)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z
O
= 50 Ω, t
r
≤ 2.5 ns, t
f
≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. t
PLH
and t
PHL
are the same as t
pd(s)
. The t
pd
propagation delay is the calculated RC time constant of the typical ON-state resistance
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
50 Ω
V
G1
V
CC
DUT
50 Ω
V
IN
50 Ω
V
G2
50 Ω
V
I
TEST
R
L
S1 V
∆
C
L
2.5 V ± 0.2 V
3.3 V ± 0.3 V
V
CC
V
I
t
PHZ
/t
PZH
t
PLZ
/t
PZL
t
pd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
2 × V
CC
2 × V
CC
GND
GND
500 Ω
500 Ω
500 Ω
500 Ω
500 Ω
500 Ω
V
CC
or GND
V
CC
or GND
GND
GND
V
CC
V
CC
30 pF
50 pF
30 pF
50 pF
30 pF
50 pF
0.15 V
0.3 V
0.15 V
0.3 V
Output
Control
(V
IN
)
Input Generator
Input Generator
V
CC
/2 V
CC
/2
V
CC
/2 V
CC
/2
V
CC
/2 V
CC
/2
V
CC
/2
V
CC
/2
V
O
SN74CB3Q16244
16-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS168 – MAY 2004 – REVISED MARCH 2005
Figure 3. Test Circuit and Voltage Waveforms
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