Datasheet

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LOGIC DIAGRAM (POSITIVE LOGIC)
1A1
SW
1B1
1A4
1OE
SW
1B4
3A1
SW
3B1
3A4
3OE
SW
3B4
47
43
1
36
32
25
2
6
13
17
2A1
SW
2B1
2A4
2OE
SW
2B4
4A1
SW
4B1
4A4
4OE
SW
4B4
41
37
48
30
26
24
8
12
19
23
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
A
EN
(1)
B
(1)
EN is the internal enable signal applied to the switch.
Charge
Pump
V
CC
SN74CB3Q16244
16-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS168 – MAY 2004 – REVISED MARCH 2005
3