Datasheet


 
    
SCDS166 − MAY 2004
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1A1
SW
1B1
1A10
1OE
SW
1B10
2A1
SW
2B1
2A10
2OE
SW
2B10
2
12
48
13
24
47
46
36
35
25
simplified schematic, each FET switch (SW)
A
EN
†
B
†
EN is the internal enable signal applied to the switch.
Charge
Pump
V
CC