Datasheet

SN54BCT8374A, SN74BCT8374A
SCAN TEST DEVICES
WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SCBS045E − JUNE 1990 − REVISED JULY 1996
10
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
bypass register
The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,
thereby reducing the number of bits per test pattern that must be applied to complete a test operation.
During Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in
Figure 4.
Bit 0
TDOTDI
Figure 4. Bypass Register Order of Scan
instruction-register opcode description
The instruction-register opcodes are shown in Table 2. The following descriptions detail the operation of
each instruction.
Table 2. Instruction-Register Opcodes
BINARY CODE
BIT 7 BIT 0
MSB LSB
SCOPE OPCODE DESCRIPTION
SELECTED DATA
REGISTER
MODE
X0000000 EXTEST/INTEST Boundary scan Boundary scan Test
X0000001 BYPASS
Bypass scan Bypass Normal
X0000010 SAMPLE/PRELOAD Sample boundary Boundary scan Normal
X0000011 INTEST/EXTEST Boundary scan Boundary scan Test
X0000100 BYPASS
Bypass scan Bypass Normal
X0000101 BYPASS
Bypass scan Bypass Normal
X0000110 HIGHZ (TRIBYP) Control boundary to high impedance Bypass Modified test
X0000111 CLAMP (SETBYP) Control boundary to 1/0 Bypass Test
X0001000 BYPASS
Bypass scan Bypass Normal
X0001001 RUNT Boundary run test Bypass Test
X0001010 READBN Boundary read Boundary scan Normal
X0001011 READBT Boundary read Boundary scan Test
X0001100 CELLTST Boundary self test Boundary scan Normal
X0001101 TOPHIP Boundary toggle outputs Bypass Test
X0001110 SCANCN Boundary-control register scan Boundary control Normal
X0001111 SCANCT Boundary-control register scan Boundary control Test
All others BYPASS Bypass scan Bypass Normal
Bit 7 is a don’t-care bit; X = don’t care.
The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the ’BCT8374A.
boundary scan
This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The BSR is
selected in the scan path. Data appearing at the device input terminals is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data that has been scanned
into the input BSCs is applied to the inputs of the normal on-chip logic, while data that has been scanned into
the output BSCs is applied to the device output terminals. The device operates in the test mode.