Datasheet

SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
parallel-signature analysis (PSA)
Data appearing at the device input terminals is compressed into a 16-bit parallel signature in the shift-register
elements of the BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the input
BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow latches of the output BSCs
remains constant and is applied to the device outputs. Figure 6 shows the 16-bit linear-feedback shift-register
algorithm through which the signature is generated. An initial seed value should be scanned into the BSR before
performing this operation.
=
1A1
1Y1
1A2 1A3 1A4 2A1 2A2 2A3 2A4
1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4
=
Figure 6. 16-Bit PSA Configuration
simultaneous PSA and PRPG (PSA/PRPG)
Data appearing at the device input terminals is compressed into an 8-bit parallel signature in the shift-register
elements of the input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the
input BSCs and applied to the inputs of the normal on-chip logic. At the same time, an 8-bit pseudo-random
pattern is generated in the shift-register elements of the output BSCs on each rising edge of TCK, updated in
the shadow latches, and applied to the device output terminals on each falling edge of TCK. Figure 7 shows
the 8-bit linear-feedback shift-register algorithm through which the signature and patterns are generated. An
initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes
will not produce additional patterns.
=
1A1
1Y1
1A2 1A3 1A4 2A1 2A2 2A3 2A4
1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4
=
Figure 7. 8-Bit PSA/PRPG Configuration