Datasheet
SCBS059B − MARCH 1989 − REVISED NOVEMBER 1993
2−7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
APPLICATION INFORMATION
A typical application circuit for a battery-buffered memory in a microcomputer system is shown in Figure 1 which uses
the SN74BCT2414. When power fails, the supply-voltage supervisor (TL7705) resets the microcomputer and
disables the memory by switching the shutdown input SD
of the memory decoder to a logic zero. All memory decoder
outputs are forced to a logic one. Abnormal write commands from the microprocessor, which may be issued during
further voltage breakdown, no longer affect the contents of the memory. When the system supply voltage becomes
lower than approximately 3.65 V, the voltage monitor inside the SN74BCT2414 memory decoder disconnects the
input buffers of this circuit from the decoding logic internally and keeps all outputs at a logic one. The VS output is
also switched off, disconnecting the system supply voltage from the memory circuits. During this low-voltage
condition, the memory decoder and the memory circuits are supplied by the battery.
CE
V
CC
SD
G
2A
1A
1B
2B
2G
V
CC
VS
8
16
A15
A14
A13
1G
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
R1
R2
R3
1 kΩ
Q1 D1
1N4148
D3
V
CC
D0 − D7
A0 − A15
DBIN
WE
RESET
Microprocessor
SN74BCT2414
A0 − A12
OE
WR
10 kΩ
0.1 µF
5 V
0.1 µF
SENSE
VREF
RES
RESIN
C
t
8- × 8K-Byte CMOS RAM
TL7705A
V
bat
V
CC
GND
For further information on this device, please contact factory.
Figure 1. Memory System With Battery Backup