Datasheet

www.ti.com
Host
AVCA406
A Side
B Side
SmartMedia/
xD-Picture
Card
V
CCA
V
CCB
SN74AVCA406
MMC, SD CARD, Memory Stick, SmartMedia, AND xD-Picture Card
± 15-kV ESD-PROTECTED VOLTAGE-TRANSLATION TRANSCEIVER
SCES615H – OCTOBER 2004 – REVISED JANUARY 2007
Configuration 4 - Interfacing With SmartMedia or xD-Picture Card
Table 10. SmartMedia or xD-Picture Card
SIGNAL NAME
PIN PIN PIN
OR PIN FUNCTION
NO. NAME TYPE
(CONNECTION)
A1 V
CCA
V
CCA
A-port supply voltage. V
CCA
powers all A-port I/Os and control inputs. Power
B1 10A1 RE.h Read enable connected to host Input
C1 9A CLE.h Command latch enable connected to host I/O
D1 9DIR (tie-low) Input pin not used in this mode. Tie to GND. Input
E1 78DIR I/O-dir.h Data direction control from host Input
F1 7A I/O7.h Data I/O 7 connected to host. Referenced to V
CCA
. I/O
G1 V
CCA
V
CCA
A-port supply voltage. V
CCA
powers all A-port I/Os and control inputs. Power
A2 2A I/O2.h Data I/O 2 connected to host. Referenced to V
CCA
. I/O
B2 3A I/O3.h Data I/O 3 connected to host. Referenced to V
CCA
. I/O
Read enable feedback to host. Used with OMAP processors. Use with other processors is
C2 10A2 RE-f.h Output
optional. Leave unconnected if not used.
D2 4A I/O4.h Data I/O 4 connected to host. Referenced to V
CCA
. I/O
E2 6A I/O6.h Data I/O 6 connected to host. Referenced to V
CCA
. I/O
F2 8A I/O8.h Data I/O 8 connected to host. Referenced to V
CCA
. I/O
G2 5A I/O5.h Data I/O 5 connected to host. Referenced to V
CCA
. I/O
A3 4DIR I/O-dir.h Data direction control connected to host Input
B3 1A I/O1.h Data I/O 1 connected to host. Referenced to V
CCA
. I/O
C3 Depopulated ball
D3 56DIR I/O-dir.h Data direction control connected to host Input
E3 GND GND Ground
F3 12A R/B.h Read/busy connected to host. Open-drain output. Output
G3 11A WP.h Write protect connected to host Input
A4 2DIR I/O-dir.h Data direction control connected to host Input
B4 1DIR I/O-dir.h Data direction control connected to host Input
C4 3DIR I/O-dir.h Data direction control connected to host Input
D4 GND GND Ground
E4 CS0 CE.h Chip enable from host Input
F4 13A WE.h Write enable from host Input
G4 CS1 ALE.h Address latch enable connected to host Input
A5 MODE1 (tie-high) Input
MODE1, MODE0 determine mode of operation (see Table 1). Tie to V
CCA
.
B5 MODE0 (tie-high) Input
23
Submit Documentation Feedback