Datasheet
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
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SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158H – DECEMBER 1998 – REVISED MARCH 2005
This 16-bit edge-triggered D-type flip-flop is operational at 1.2-V to 3.6-V V
CC
, but is designed specifically for
1.65-V to 3.6-V V
CC
operation.
The SN74AVC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,
and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the
clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs. OE can be used to
place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the
high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state
and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16374 is characterized for operation from –40 ° C to 85 ° C.
TERMINAL ASSIGNMENTS
(1)
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A 1 OE NC NC NC NC 1CLK
B 1Q2 1Q1 GND GND 1D1 1D2
C 1Q4 1Q3 V
CC
V
CC
1D3 1D4
D 1Q6 1Q5 GND GND 1D5 1D6
E 1Q8 1Q7 1D7 1D8
F 2Q1 2Q2 2D2 2D1
G 2Q3 2Q4 GND GND 2D4 2D3
H 2Q5 2Q6 V
CC
V
CC
2D6 2D5
J 2Q7 2Q8 GND GND 2D8 2D7
K 2 OE NC NC NC NC 2CLK
(1) NC - No internal connection
2