Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Standard Non-inverting VFSOP 8

Switching Characteristics

at 25 MHz

(A)

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0 5

10 15

35 40 45

Time (ns)

Voltage (V)

OutputInput

(A)

SN74AUP2Gxx data at C = 15 pF.

(A)

Single, dual, and triple gates

Static-Power Consumption

(

µA)

AUP

3.3-V

Logic

(A)

20%

40%

60%

80%

100%

Dynamic-Power Consumption

(

pF)

AUP

3.3-V

Logic

(A)

20%

40%

60%

80%

100%

DCU PACKAGE

(TOP VIEW)

3 6

1CLK

GND

2CLK

RSE PACKAGE

(TOP VIEW)

2CLK

GND

1CLK

YFP PACKAGE

(TOP VIEW)

3 6

1CLK

GND

2CLK

3 6

1CLK

GND

2CLK

DQE PACKAGE

(TOP VIEW)

C1 C2

B1 B2

A1 A2

SN74AUP2G79

www.ti.com

SCES755C –DECEMBER 2009–REVISED JULY 2012

LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP

Check for Samples: SN74AUP2G79

FEATURES

• Available in the Texas Instruments NanoStar™

• Optimized for 3.3-V Operation

Package

• 3.6-V I/O Tolerant to Support Mixed-Mode

• Low Static-Power Consumption Signal Operation

= 0.9 μA Maximum)

• t

= 4 ns Maximum at 3.3 V

• Low Dynamic-Power Consumption

• Suitable for Point-to-Point Applications

= 3 pF Typ at 3.3 V)

• Latch-Up Performance Exceeds 100 mA Per

• Low Input Capacitance (C

= 1.5 pF Typical)

JESD 78, Class II

• Low Noise – Overshoot and Undershoot

• ESD Performance Tested Per JESD 22

<10% of V

– 2000-V Human-Body Model

• I

off

Supports Partial-Power-Down Mode

(A114-B, Class II)

Operation

– 1000-V Charged-Device Model (C101)

• Wide Operating V

Range of 0.8 V to 3.6 V

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION

The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable

applications. This family ensures a very low static- and dynamic-power consumption across the entire V

range

of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal

integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

Figure 1. AUP – The Lowest-Power Family Figure 2. Excellent Signal Integrity

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2NanoStar is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (23 pages)

PAGE 1
SN74AUP2G79 www.ti.com SCES755C – DECEMBER 2009 – REVISED JULY 2012 LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP Check for Samples: SN74AUP2G79 FEATURES 1 • 2 • • • • • • • • Available in the Texas Instruments NanoStar™ Package Low Static-Power Consumption (ICC = 0.9 μA Maximum) Low Dynamic-Power Consumption (Cpd = 3 pF Typ at 3.3 V) Low Input Capacitance (Ci = 1.
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SN74AUP2G79 SCES755C – DECEMBER 2009 – REVISED JULY 2012 www.ti.com When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
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SN74AUP2G79 www.ti.com SCES755C – DECEMBER 2009 – REVISED JULY 2012 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 4.6 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 4.6 V VO Output voltage range in the high or low state (2) –0.5 VCC + 0.
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SN74AUP2G79 SCES755C – DECEMBER 2009 – REVISED JULY 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VCC = 0.8 V VIH High-level input voltage MIN MAX 0.8 3.6 VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V 0.65 × VCC V 1.6 2 VCC = 0.8 V Low-level input voltage V VCC VCC = 3 V to 3.6 V VIL UNIT 0 VCC = 1.1 V to 1.95 V 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.9 V VI Input voltage 0 3.6 VO Output voltage 0 VCC V VCC = 0.
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SN74AUP2G79 www.ti.com SCES755C – DECEMBER 2009 – REVISED JULY 2012 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS VCC MIN TYP TA = –40°C to 85°C MAX MIN IOH = –20 μA 0.8 V to 3.6 V VCC – 0.1 VCC – 0.1 IOH = –1.1 mA 1.1 V 0.75 × VCC 0.7 × VCC IOH = –1.7 mA 1.4 V 1.11 1.03 IOH = –1.9 mA 1.65 V 1.32 1.3 2.05 1.97 1.9 1.85 2.72 2.67 IOH = –2.3 mA 2.3 V IOH = –3.1 mA IOH = –2.
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SN74AUP2G79 SCES755C – DECEMBER 2009 – REVISED JULY 2012 www.ti.com TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4) VCC fclock Clock frequency TA = 25°C TA = –40°C to 85°C TYP MIN MAX 0.8 V 20 1.2 V ± 0.1 V 80 1.5 V ± 0.1 V 100 1.8 V ± 0.15 V 140 2.5 V ± 0.2 V 210 3.3 V ± 0.3 V tw Pulse duration, CLK high or low Data high tsu 4.8 1.2 V ± 0.1 V 2.2 1.5 V ± 0.1 V 1.5 1.8 V ± 0.15 V 1.6 2.5 V ± 0.2 V 1.7 3.
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SN74AUP2G79 www.ti.com SCES755C – DECEMBER 2009 – REVISED JULY 2012 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd CLK Q TA = –40°C to 85°C TA = 25°C VCC MIN TYP MAX MIN 0.8 V 93 90 1.2 V ± 0.1 V 199 220 1.5 V ± 0.1 V 250 230 1.8 V ± 0.15 V 271 240 2.5 V ± 0.2 V 280 250 3.3 V ± 0.3 V 280 260 0.8 V 15.9 UNIT MAX MHz 1.2 V ± 0.
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SN74AUP2G79 SCES755C – DECEMBER 2009 – REVISED JULY 2012 www.ti.com SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd CLK Q TA = –40°C to 85°C TA = 25°C VCC MIN TYP MAX MIN 0.8 V 48 30 1.2 V ± 0.1 V 112 120 1.5 V ± 0.1 V 151 160 1.8 V ± 0.15 V 194 220 2.5 V ± 0.2 V 248 250 3.3 V ± 0.3 V 280 260 0.8 V 20.3 UNIT MAX MHz 1.2 V ± 0.
PAGE 9
SN74AUP2G79 www.ti.com SCES755C – DECEMBER 2009 – REVISED JULY 2012 PARAMETER MEASUREMENT INFORMATION (Propagation Delays, Setup and Hold Times, and Pulse Width) From Output Under Test CL (see Note A) 1 MΩ LOAD CIRCUIT CL VM VI VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.
PAGE 10
SN74AUP2G79 SCES755C – DECEMBER 2009 – REVISED JULY 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION (Enable and Disable Times) 2 x V CC S1 5 kΩ From Output Under Test GND CL (see Note A) 5 kΩ TEST S1 tPLZ/tPZL tPHZ/tPZH 2 x V CC GND LOAD CIRCUIT CL VM VI V∆ VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.
PAGE 11
SN74AUP2G79 www.ti.com SCES755C – DECEMBER 2009 – REVISED JULY 2012 REVISION HISTORY Changes from Revision B (March 2010) to Revision C • Page Added clock high to FUNCTION TABLE. .............................................................................................................................
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Sep-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74AUP2G79DCUR US8 DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 SN74AUP2G79DQER X2SON DQE 8 5000 180.0 8.4 1.2 1.6 0.55 4.0 8.0 Q1 SN74AUP2G79RSER UQFN RSE 8 5000 180.0 8.4 1.6 1.6 0.66 4.0 8.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 8-Sep-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AUP2G79DCUR US8 DCU 8 3000 202.0 201.0 28.0 SN74AUP2G79DQER X2SON DQE 8 5000 202.0 201.0 28.0 SN74AUP2G79RSER UQFN RSE 8 5000 202.0 201.0 28.0 SN74AUP2G79YFPR DSBGA YFP 8 3000 220.0 220.0 35.
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D: Max = 1.59 mm, Min = 1.53 mm E: Max = 0.79 mm, Min = 0.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.