Datasheet

1A 1Y

1 6

2A 2Y

3 4

SN74AUP2G04

SCES747B –SEPTEMBER 2009–REVISED MARCH 2010

www.ti.com

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

(1)

ORDERABLE TOP-SIDE

PACKAGE

(2)

PART NUMBER MARKING

(3)

NanoStar™ – WCSP (DSBGA)

Reel of 3000 SN74AUP2G04YFPR _ _ _ H C _

0.23-mm Large Bump – YFP (Pb-free)

QFN – DRY Reel of 5000 SN74AUP2G04DRYR H4

–40°C to 85°C

uQFN – DSF Reel of 5000 SN74AUP2G04DSFR H4

SOT (SC-70) – DCK Reel of 3000 SN74AUP2G04DCKR H4_

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) DCK: The actual top-side marking has one additional character that designates the wafer fab/assembly site.

YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

FUNCTION TABLE

(Each Inverter)

INPUT OUTPUT

A Y

H L

L H

LOGIC DIAGRAM (POSITIVE LOGIC)

Product Folder Link(s): SN74AUP2G04