Datasheet

1
2
3
6
5
4
Y
C
V
CC
YC
GND
1
2
3
6
5
4
B
Y
C
V
CC
C
Y
B
GND
C
Y
B
C
Y
B
1
2
3
6
5
4
B
Y
C
V
CC
GND
1
2
3
6
5
4
A
Y
C
V
CC
C
Y
A
C
Y
A
GND
SN74AUP1T98
www.ti.com SCES614I –OCTOBER 2004–REVISED MAY 2013
Figure 7. 14+02/14+08: 2-Input NOR Gate With One Inverted Input
2-Input NAND Gate With One Inverted Input
Figure 8. 14+00/14+32: 2-Input NAND Gate With One Inverted Input
2-Input NOR Gate With One Inverted Input
Figure 9. 32: 2-Input NOR Gate
Figure 10. 17/34: Noninverted Buffer
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