Datasheet

AUP
LVC
AUP
AUP
LVC
Static-Power Consumption
(µA)
Dynamic-Power Consumption
(pF)
†
Single, dual, and triple gates
3.3-V
Logic
†
3.3-V
Logic
†
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
0 5
10 15 20
25
30
35 40 45
Time − ns
Voltage − V
†
AUP1G08 data at C
L
= 15 pF
Switching Characteristics
at 25 MHz
†
OutputInput
SN74AUP1T97
SCES613I –OCTOBER 2004–REVISED MAY 2010 www.ti.com
I
off
is a feature that allows for powered-down conditions (V
CC
= 0 V) and is important in portable and mobile
applications. When V
CC
= 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of
the device. No damage occurs to the device under these conditions.
The SN74AUP1T97 is designed with optimized current-drive capability of 4 mA to reduce line reflections,
overshoot, and undershoot caused by high-drive outputs.
NanoStar package technology is a major breakthrough in IC packaging concepts, using the die as the package.
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(3)
NanoStar™ – WCSP (DSBGA)
Reel of 3000 SN74AUP1T97YZPR _ _ _TH_
0.23-mm Large Bump – YZP (Pb-free)
NanoStar™ – WCSP (DSBGA)
Reel of 3000 SN74AUP1T97YFPR _ _ _TH_
0.23-mm Large Bump – YFP
–40°C to 85°C
QFN – DRY Reel of 5000 SN74AUP1T97DRYR TH
uQFN – DSF Reel of 5000 SN74AUP1T97DSFR TH
SOT (SOT-23) – DBV Reel of 3000 SN74AUP1T97DBVR HT4_
SOT (SC-70) – DCK Reel of 3000 SN74AUP1T97DCKR TH_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DBV/DCK: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ● = Pb-free).
FUNCTION SELECTION TABLE
LOGIC FUNCTION FIGURE NO.
2-to-1 data selector 5
2-input AND gate 6
2-input OR gate with one inverted input 7
2-input NAND gate with one inverted input 7
2-input AND gate with one inverted input 8
2-input NOR gate with one inverted input 8
2-input OR gate 9
Inverter 10
Noninverted buffer 11
Figure 1. AUP – The Lowest-Power Family Figure 2. Excellent Signal Integrity
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