Datasheet

3
1
6
C
B
A
4
Y
B
Y
C
1
2
3
6
5
4
B
Y
C
V
CC
B
Y
C
B
Y
C
1
2
3
6
5
4
B
Y
C
V
CC
B
Y
C
SN74AUP1T58
SCES612H –OCTOBER 2004–REVISED MARCH 2010 www.ti.com
FUNCTION TABLE
INPUTS
OUTPUT
Y
C B A
L L L L
L L H H
L H L L
L H H H
H L L H
H L H H
H H L L
H H H L
LOGIC DIAGRAM (POSITIVE LOGIC)
LOGIC CONFIGURATIONS
Figure 5. 00/14+32: 2-Input NAND Gate 2-Input OR Gate With Both Inputs Inverted
Figure 6. 14+08/14+02: 2-Input AND Gate With Inverted B Input
2-Input NOR Gate With Inverted Input
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