Datasheet

1
3
4
C
B
A
6
Y
AUP
LVC
AUP
AUP
LVC
Static-Power Consumption
(µA)
Dynamic-Power Consumption
(pF)
†
Single, dual, and triple gates
3.3-V
Logic
†
3.3-V
Logic
†
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
0 5
10 15 20
25
30
35 40 45
Time − ns
Voltage − V
†
AUP1G08 data at C
L
= 15 pF
Switching Characteristics
at 25 MHz
†
OutputInput
1.8-V
System
3.3-V
System
V
IH
= 1.19 V
V
IL
= 0.5 V
3.3 V
2.5-V
System
3.3-V
System
V
IH
= 1.19 V
V
IL
= 0.5 V
3.3 V
1.8-V
System
2.5-V
System
V
IH
= 1.10 V
V
IL
= 0.35 V
2.5 V
3.3-V
System
2.5-V
System
V
IH
= 1.10 V
V
IL
= 0.35 V
2.5 V
SN74AUP1T157
www.ti.com SCES807 –APRIL 2010
LOGIC DIAGRAM (BUFFER MULTIPLEXER)
Figure 2. AUP – The Lowest-Power Family Figure 3. Excellent Signal Integrity
Figure 4. Typical Design Examples
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