Datasheet

2
4
A
Y
AUP
LVC
AUP
AUP
LVC
Static-Power Consumption
(µA)
Dynamic-Power Consumption
(pF)
†
Single, dual, and triple gates
3.3-V
Logic
†
3.3-V
Logic
†
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
0 5
10 15 20
25
30
35 40 45
Time − ns
Voltage − V
†
AUP1G08 data at C
L
= 15 pF
Switching Characteristics
at 25 MHz
†
OutputInput
SN74AUP1T14
SCES802 –APRIL 2010 www.ti.com
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(3)
Reel of 3000 SN74AUP1T14DCKR
–40°C to 85°C SOT (SC-70) – DCK 6F_
Reel of 250 SN74AUP1T14DCKT
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) The actual top-side marking has one additional character that designates the wafer fab/assembly site.
FUNCTION TABLE
INPUT OUTPUT
(Lower Level Input) (V
CC
CMOS)
A Y
H L
L H
Supply V
CC
= 2.3 V to 2.7 V (2.5 V)
INPUTS
OUTPUT
V
T+
max = V
IH
min
CMOS
V
T-
min = V
IL
max
A B Y
V
IH
= 1.1 V V
OH
= 1.85 V
V
IL
= 0.35 V V
OL
= 0.45 V
Supply V
CC
= 3 V to 3.6 V (3.3 V)
INPUTS
OUTPUT
V
T+
max = V
IH
min
CMOS
V
T-
min = V
IL
max
A B Y
V
IH
= 1.19 V V
OH
= 2.55 V
V
IL
= 0.5 V V
OL
= 0.45 V
LOGIC DIAGRAM (SCHMITT-TRIGGER INVERTER GATE)
Figure 1. AUP – The Lowest-Power Family Figure 2. Excellent Signal Integrity
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