Datasheet

1
2
3
6
5
4
A
Y
C
V
CC
C
Y
A
C
Y
A
GND
C
Y
B
C
Y
B
1
2
3
6
5
4
B
Y
C
V
CC
GND
1
2
3
6
5
4
B
Y
C
V
CC
C
Y
B
GND
1
2
3
6
5
4
Y
C
V
CC
YC
GND
SN74AUP1G98
SCES506H –NOVEMBER 2003–REVISED MAY 2010 www.ti.com
Figure 5. 2-Input NOR Gate With One Inverted Input
2-Input AND Gate With One Inverted Input
Figure 6. 2-Input NAND Gate With One Inverted Input
2-Input OR Gate With One Inverted Input
Figure 7. 2-Input NOR Gate
Figure 8. Noninverted Buffer
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