Datasheet
1
2
4
A
B
Y
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
0 5
10 15
20
25
30
35 40 45
Time − ns
Voltage − V
†
AUP1G08 data at C
L
= 15 pF
OutputInput
Switching Characteristics
at 25 MHz
†
AUP
LVC
AUP
AUP
LVC
Static-Power Consumption
(µA)
Dynamic-Power Consumption
(pF)
†
Single, dual, and triple gates
3.3-V
Logic
†
3.3-V
Logic
†
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
SN74AUP1G32
SCES580H –JUNE 2004–REVISED AUGUST 2012
www.ti.com
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Figure 1. AUP–The Lowest-Power Family Figure 2. Excellent Signal Integrity
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(3)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YFP (Pb- Reel of 3000 SN74AUP1G32YFPR _ _ _HG_
free)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb- Reel of 3000 SN74AUP1G32YZPR _ _ _HG_
free)
QFN – DRY Reel of 5000 SN74AUP1G32DRYR HG
QFN – DRY Reel of 5000 SN74AUP1G32DRY2
(4)
HG
–40°C to 85°C
uQFN – DSF Reel of 5000 SN74AUP1G32DSFR HG
uQFN – DSF2 Reel of 5000 SN74AUP1G32DSF2
(4)
HG
Reel of 3000 SN74AUP1G32DBVR
SOT (SOT-23) – DBV H32_
Reel of 250 SN74AUP1G32DBVT
Reel of 3000 SN74AUP1G32DCKR
SOT (SC-70) – DCK HG_
Reel of 250 SN74AUP1G32DCKT
SOT (SOT-553) – DRL Reel of 4000 SN74AUP1G32DRLR HG_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
(4) Pin 1 orientation at quadrant 3 in Tape.
FUNCTION TABLE
INPUTS OUTPUT
Y
A B
L L L
L H H
H L H
H H H
LOGIC DIAGRAM (POSITIVE LOGIC)
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Product Folder Links: SN74AUP1G32