Datasheet
1
2
4
A
B
Y
Y + A • B or Y + A ) B
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
0 5
10 15
20
25
30
35 40 45
Time − ns
Voltage − V
†
AUP1G08 data at C
L
= 15 pF
OutputInput
Switching Characteristics
at 25 MHz
†
AUP
LVC
AUP
AUP
LVC
Static-Power Consumption
(µA)
Dynamic-Power Consumption
(pF)
†
Single, dual, and triple gates
3.3-V
Logic
†
3.3-V
Logic
†
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
SN74AUP1G08
SCES502N –NOVEMBER 2003 –REVISED NOVEMBER 2012
www.ti.com
Figure 1. AUP – The Lowest-Power Family Figure 2. Excellent Signal Integrity
This single 2-input positive-AND gate performs the Boolean function in positive logic.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
(1)
ORDERABLE TOP-SIDE
T
A
PACKAGE
(2)
PART NUMBER MARKING
(3)
NanoStar™ – WCSP (DSBGA)
Reel of 3000 SN74AUP1G08YFPR _ _ _HE_
0.23-mm Large Bump – YFP (Pb-free)
NanoStar™ – WCSP (DSBGA)
Reel of 3000 SN74AUP1G08YZPR _ _ _HE_
0.23-mm Large Bump – YZP (Pb-free)
QFN – DRY Reel of 5000 SN74AUP1G08DRYR HE
SN74AUP1G08DSFR
–40°C to 85°C
uQFN – DSF Reel of 5000 HE
SN74AUP1G08DSF2
(4)
uQFN – DPW Reel of 5000 SN74AUP1G08DPWR HE
SOT (SOT-23) – DBV Reel of 3000 SN74AUP1G08DBVR H08_
SOT (SC-70) – DCK Reel of 3000 SN74AUP1G08DCKR
HE_
SOT (SOT-553) – DRL Reel of 4000 SN74AUP1G08DRLR
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
(4) Pin 1 orientation at quadrant 3 in Tape.
FUNCTION TABLE
INPUTS
OUTPUT
Y
A B
L L L
L H L
H L L
H H H
LOGIC DIAGRAM (POSITIVE LOGIC)
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Product Folder Links: SN74AUP1G08