Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Standard Inverted SC 70 5

www.ti.com

FEATURES

CLK

GND

DBVPACKAGE

(TOP VIEW)

D V

CLK

GND

CLK

Seemechanicaldrawingsfordimensions.

DCKPACKAGE

(TOP VIEW)

YZP PACKAGE

(BOTTOMVIEW)

DESCRIPTION/ORDERING INFORMATION

SN74AUC1G80

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

SCES388K – MARCH 2002 – REVISED JANUARY 2007

• Available in the Texas Instruments • Low Power Consumption, 10- µ A Max I

NanoFree™ Package

• ± 8-mA Output Drive at 1.8 V

• Optimized for 1.8-V Operation and Is 3.6-V

• Latch-Up Performance Exceeds 100 mA Per

I/O Tolerant to Support Mixed-Mode Signal

JESD 78, Class II

Operation

• ESD Protection Exceeds JESD 22

• I

off

Supports Partial-Power-Down Mode

– 2000-V Human-Body Model (A114-A)

Operation

– 200-V Machine Model (A115-A)

• Sub-1-V Operable

– 1000-V Charged-Device Model (C101)

• Max t

of 1.9 ns at 1.8 V

This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V V

, but is designed

specifically for 1.65-V to 1.95-V V

operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the

positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the

rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without

affecting the levels at the outputs.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

(2)

NanoFree™ – WCSP (DSBGA)

0.23-mm Large Bump – YZP Reel of 3000 SN74AUC1G80YZPR _ _ _UX_

(Pb-free)

–40 ° C to 85 ° C

SOT (SOT-23) – DBV Reel of 3000 SN74AUC1G80DBVR U80_

SOT (SC-70) – DCK Reel of 3000 SN74AUC1G80DCKR UX_

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.

YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (15 pages)

PAGE 1
SN74AUC1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES388K – MARCH 2002 – REVISED JANUARY 2007 FEATURES • • • • • • • • Available in the Texas Instruments NanoFree™ Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 1.9 ns at 1.8 V • DBV PACKAGE (TOP VIEW) D 1 CLK 2 GND 3 5 4 Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 1.
PAGE 2
SN74AUC1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES388K – MARCH 2002 – REVISED JANUARY 2007 FUNCTION TABLE INPUTS OUTPUT Q CLK D ↑ H L ↑ L H L X Q0 LOGIC DIAGRAM (POSITIVE LOGIC) CLK CLK Q Q D D Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 3.6 V range (2) VI Input voltage –0.5 3.
PAGE 3
SN74AUC1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES388K – MARCH 2002 – REVISED JANUARY 2007 Recommended Operating Conditions VCC (1) Supply voltage VCC = 0.8 V VIH High-level input voltage MIN MAX 0.8 2.7 UNIT V VCC VCC = 1.1 V to 1.95 V 0.65 × VCC VCC = 2.3 V to 2.7 V V 1.7 VCC = 0.8 V 0 0.35 × VCC VIL Low-level input voltage VCC = 1.1 V to 1.95 V VI Input voltage 0 3.6 V VO Output voltage 0 VCC V VCC = 2.3 V to 2.
PAGE 4
SN74AUC1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES388K – MARCH 2002 – REVISED JANUARY 2007 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 0.8 V TYP VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN MAX MIN MAX MIN MAX MIN MAX 200 fclock Clock frequency 50 tw Pulse duration, CLK high or low 4.6 1.7 1.7 1.7 1.
PAGE 5
SN74AUC1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES388K – MARCH 2002 – REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 2 × VCC S1 RL From Output Under Test Open S1 Open 2 × VCC GND GND CL (see Note A) RL LOAD CIRCUIT VCC CL RL VD 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF 2 kW 2 kW 2 kW 2 kW 2 kW 1 kW 500 W 0.1 V 0.1 V 0.1 V 0.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ SOT-23 DBV 5 3000 180.0 8.4 SN74AUC1G80DCKR SC70 DCK 5 3000 178.0 9.0 2.4 SN74AUC1G80YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 SN74AUC1G80DBVR Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) Pack Materials-Page 1 3.23 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.17 1.37 4.0 8.0 Q3 2.5 1.2 4.0 8.0 Q3 1.52 0.63 4.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AUC1G80DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 SN74AUC1G80DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74AUC1G80YZPR DSBGA YZP 5 3000 220.0 220.0 35.
PAGE 10
PAGE 11
PAGE 12
PAGE 13
PAGE 14
D: Max = 1.418 mm, Min =1.357 mm E: Max = 0.918 mm, Min =0.
PAGE 15
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.