Datasheet

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DBVPACKAGE
(TOP VIEW)
3
2
4
51
OE V
CC
Y
A
GND
Seemechanicaldrawingsfordimensions.
NC Nointernalconnection
V
CC
3
2
4
51
OE
Y
A
GND
DCKPACKAGE
(TOP VIEW)
V
CC
OE
GND
Y
A
1
4
2
3
5
YZP PACKAGE
(BOTTOMVIEW)
DRY PACKAGE
(TOP VIEW)
A
OE
6
4
2
3
GND
Y
V
CC
1
5
NC
P
R
EVIE
W
DESCRIPTION/ORDERING INFORMATION
SN74AUC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES383J MARCH 2002 REVISED JULY 2007
Available in the Texas Instruments Low Power Consumption, 10- μ A Max I
CC
NanoFree™ Package
± 8-mA Output Drive at 1.8 V
Optimized for 1.8-V Operation and Is 3.6-V I/O
Latch-Up Performance Exceeds 100 mA Per
Tolerant to Support Mixed-Mode Signal
JESD 78, Class II
Operation
ESD Protection Exceeds JESD 22
I
off
Supports Partial-Power-Down Mode
2000-V Human-Body Model (A114-A)
Operation
200-V Machine Model (A115-A)
Sub-1-V Operable
1000-V Charged-Device Model (C101)
Max t
pd
of 2.5 ns at 1.8 V
This bus buffer gate is operational at 0.8-V to 2.7-V V
CC
, but is designed specifically for 1.65-V to 1.95-V V
CC
operation.
The SN74AUC1G126 is a single line driver with a 3-state output. The output is disabled when the output-enable
(OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
PACKAGE
(1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(3)
NanoFree™
Reel of 3000 SN74AUC1G126YZPR _ _ _UN_
WCSP (DSBGA) YZP (Pb-free)
SON DRY Reel of 5000 SN74AUC1G126DRYR PREVIEW
–40 ° C to 85 ° C
SOT (SOT-23) DBV Reel of 3000 SN74AUC1G126DBVR U26_
SOT (SC-70) DCK Reel of 3000 SN74AUC1G126DCKR UN_
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com .
(3) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
Copyright © 2002–2007, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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