Datasheet
SDAS038C − DECEMBER 1982 − REVISED DECEMBER 1994
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
APPLICATION INFORMATION
A
B
C
D
E
F
G
H
I
Σ EVEN
Σ ODD
A
B
C
D
E
F
G
H
I
Σ EVEN
Σ ODD
A
B
C
D
E
F
G
H
I
Σ EVEN
Σ ODD
H - Even
L = Odd
H - Odd
L = Even
A
B
C
D
E
F
G
H
I
Σ ODD
A
B
C
D
E
F
G
H
I
Σ ODD
A
B
C
D
E
F
G
H
I
Σ ODD
H - Even
L = Odd
H - Odd
L = Even
To Other
SN74AS280s
A
B
C
D
E
F
G
H
I
Σ EVEN
Σ ODD
25-LINE
PARITY GENERATOR/CHECKER
81-LINE
PARITY GENERATOR/CHECKER
Three SN74ALS280/SN74AS280 devices can be
used to implement a 25-line parity generator/
checker.
As an alternative, the Σ ODD outputs of two or three
parity generators/checkers can be decoded with a
2-input (′AS86A or ′ALS86) exclusive-OR gate for
18- or 27-line parity applications.
Longer word lengths can be implemented by cascading SN74ALS280/SN74AS280
devices. Parity can be generated for word lengths up to 81 bits.