Datasheet

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SDAS212A − DECEMBER 1983 − REVISED DECEMBER 1994
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
MODE
CLK
SERIAL PARALLEL
Q
A
Q
B
Q
C
Q
D
CLR
S1 S0
CLK
LEFT RIGHT A B C D
Q
A
Q
B
Q
C
Q
D
L X X X X X X X X X L L L L
H X XLX XXXXXQ
A0
Q
B0
Q
C0
Q
D0
H H H ↑ X Xabcdabcd
H L H ↑ X HXXXXHQ
An
Q
Bn
Q
Cn
H L H ↑ X LXXXXLQ
An
Q
Bn
Q
Cn
H H L ↑ H XXXXXQ
Bn
Q
Cn
Q
Dn
H
H H L ↑ L XXXXXQ
Bn
Q
Cn
Q
Dn
L
H L L X X X X X X X Q
A0
Q
B0
Q
C0
Q
D0
H = high level (steady state); L = low level (steady state); X = irrelevant (any input, including transitions); ↑ = transition from
low to high level; a, b, c, d = the level of steady-state input at inputs A, B, C, or D, respectively; Q
A0
, Q
B0
, Q
C0
, Q
D0
= the
level of Q
A
, Q
B
, Q
C
, or Q
D
, respectively, before the indicated steady-state input conditions were established; Q
An
, Q
Bn
, Q
Cn
,
Q
Dn
= the level of Q
A
, Q
B
, Q
C
, respectively, before the most recent ↑ transition of the clock.
logic symbol
†
SRG4
3, 4D
4
B
3, 4D
5
C
3, 4D
6
D
2, 4D
7
SL SER
1, 4D
2
SR SER
3, 4D
3
A
R
1
11
CLK
C4
M
0
3
14
13
15
1
10
S1
0
9
S0
1 /2
12
CLR
Q
A
Q
B
Q
C
Q
D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.