Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Standard Three-state, Non-inverting TFSOP 48

www.ti.com

FEATURES

SN54ALVTH16374...WDPACKAGE

PACKAGE

(TOP VIEW)

SN74ALVTH16374...DGG,DGV,ORDL

1OE

1CLK

1Q1 1D1

1Q2

1D2

GND

1Q3 1D3

1Q4 1D4

1Q5 1D5

1Q6 1D6

GND GND

1Q7 1D7

1Q8

2Q1

2Q2

GND

2Q3

2Q4

2Q5

2Q6

GND

2Q7

2Q8

2OE

1D8

2D1

2D2

GND

2D3

2D4

2D5

2D6

GND

2D7

2D8

2CLK

481

454

436

409

3910

3811

DESCRIPTION/ORDERING INFORMATION

SN54ALVTH16374 , , SN74ALVTH16374

2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCES068G – JUNE 1996 – REVISED NOVEMBER 2006

• State-of-the-Art Advanced BiCMOS

Technology (ABT) Widebus™ Design for 2.5-V

and 3.3-V Operation and Low Static Power

Dissipation

• Support Mixed-Mode Signal Operation

(5-V Input and Output Voltages With 2.3-V to

3.6-V V

)

• Typical V

OLP

(Output Ground Bounce) <0.8 V

at V

= 3.3 V, T

= 25°C

• High Drive (–24/24 mA at 2.5-V V

and –32/64

mA at 3.3-V )

• Power Off Disables Outputs, Permitting Live

Insertion

• High-Impedance State During Power Up and

Power Down Prevents Driver Conflict

• Uses Bus Hold on Data Inputs in Place of

External Pullup/Pulldown Resistors to Prevent

the Bus From Floating

• Auto3-State Eliminates Bus Current Loading

When Output Exceeds V

+ 0.5 V

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Protection

– Exceeds 2000 V Per MIL-STD-883, Method

3015

– Exceeds 200 V Using Machine Model

– Exceeds 1000 V Using Charged-Device

Model, Robotic Method

• Flow-Through Architecture Facilitates Printed

Circuit Board Layout

• Distributed V

and GND Pin Configuration

Minimizes High-Speed Switching Noise

• Package Options Include Plastic Shrink

Small-Outline (DL), Thin Shrink Small-Outline

(DGG), Thin Very Small-Outline (DGV)

Packages, and 380-mil Fine-Pitch Ceramic Flat

(WD) Package

The 'ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V or

3.3-V V

operation, but with the capability to provide a TTL interface to a 5-V system environment. These

devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and

working registers.

These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock

(CLK), the flip-flops store the logic levels set up at the data (D) inputs.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

UNLESS OTHERWISE NOTED this document contains

PRODUCTION DATA information current as of publication date.

Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (21 pages)

PAGE 1
SN54ALVTH16374,, SN74ALVTH16374 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS www.ti.com FEATURES • • • • • • • • • • • • • State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus™ Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC) Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C High Drive (–24/24 mA at 2.5-V VCC and –32/64 mA at 3.
PAGE 2
SN54ALVTH16374,, SN74ALVTH16374 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS www.ti.com SCES068G – JUNE 1996 – REVISED NOVEMBER 2006 DESCRIPTION/ORDERING INFORMATION (CONTINUED) A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
PAGE 3
SN54ALVTH16374,, SN74ALVTH16374 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS www.ti.
PAGE 4
SN54ALVTH16374,, SN74ALVTH16374 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS www.ti.com SCES068G – JUNE 1996 – REVISED NOVEMBER 2006 LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1CLK 1D1 1 2OE 48 2CLK C1 47 2 1D 1Q1 24 25 C1 2D1 36 To Seven Other Channels 13 1D 2Q1 To Seven Other Channels Pin numbers shown are for the DGG, DL, and WD packages.
PAGE 5
www.ti.com SN54ALVTH16374,, SN74ALVTH16374 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCES068G – JUNE 1996 – REVISED NOVEMBER 2006 Recommended Operating Conditions (1) VCC = 2.5 V ± 0.2 V SN54ALVTH16374 (2) MIN VCC Supply voltage 2.3 VIH High-level input voltage 1.7 VIL Low-level input voltage VI Input voltage IOH High-level output current Low-level output current IOL 0 MIN TYP MAX 2.7 2.3 2.7 1.
PAGE 6
SN54ALVTH16374,, SN74ALVTH16374 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS www.ti.com SCES068G – JUNE 1996 – REVISED NOVEMBER 2006 Electrical Characteristics over operating free-air temperature range VCC = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 2.3 V, VCC = 2.3 V MIN TYP (2) II = –18 mA VCC = 2.3 V to 2.7 V, IOH = –100 µA VOH SN54ALVTH16374 (1) IOH = –6 mA –1.2 –1.2 1.8 0.2 0.2 0.4 IOL = 8 mA 0.4 IOL = 18 mA Data inputs 0.
PAGE 7
SN54ALVTH16374,, SN74ALVTH16374 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS www.ti.com SCES068G – JUNE 1996 – REVISED NOVEMBER 2006 Electrical Characteristics over recommended operating free-air temperature range VCC = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS SN54ALVTH16374 (1) MIN TYP (2) VCC = 3 V, II = –18 mA VCC = 3 V to 3.6 V, IOH = –100 µA VCC – 0.2 IOH = –24 mA 2 VCC = 3 V VCC = 3 V to 3.
PAGE 8
SN54ALVTH16374,, SN74ALVTH16374 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS www.ti.com SCES068G – JUNE 1996 – REVISED NOVEMBER 2006 Timing Requirements over recommended operating free-air temperature range VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) SN54ALVTH16374 (1) MIN fclock Clock frequency tw Pulse duration, CLK high or low tsu Setup time, data before CLK↑ th Hold time, data after CLK↑ (1) MAX SN74ALVTH16374 MIN 150 MAX UNIT 150 1.5 1.
PAGE 9
SN54ALVTH16374,, SN74ALVTH16374 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS www.ti.com SCES068G – JUNE 1996 – REVISED NOVEMBER 2006 Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER TO (OUTPUT) SN54ALVTH16374 (1) MIN SN74ALVTH16374 MAX MIN MAX fmax 150 tPLH 1.4 3.9 1.5 3.8 1.4 3.9 1.5 3.8 1 4.2 1 4.1 1 3.8 1 3.7 1.7 4.3 1.8 4.2 1 3.
PAGE 10
SN54ALVTH16374,, SN74ALVTH16374 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS www.ti.com SCES068G – JUNE 1996 – REVISED NOVEMBER 2006 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 11
SN54ALVTH16374,, SN74ALVTH16374 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS www.ti.com SCES068G – JUNE 1996 – REVISED NOVEMBER 2006 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ±0.3 V 6V 500 W From Output Under Test S1 TEST Open GND CL = 50 pF (see Note A) S1 Open 6V tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 W GND tW LOAD CIRCUIT 3V 3V Timing Input Input 1.5 V 1.5 V 1.5 V 0V tsu 0V VOLTAGE WAVEFORMS PULSE DURATION th 3V Data Input 1.5 V 1.
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 9-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device 74ALVTH16374ZQLR Package Package Pins Type Drawing BGA MI CROSTA R JUNI OR SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 SN74ALVTH16374DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 SN74ALVTH16374GR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 9-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74ALVTH16374ZQLR BGA MICROSTAR JUNIOR ZQL 56 1000 333.2 345.9 28.6 SN74ALVTH16374DLR SSOP DL 48 1000 367.0 367.0 55.0 SN74ALVTH16374GR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74ALVTH16374VR TVSOP DGV 48 2000 367.0 367.0 38.
PAGE 16
PAGE 17
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 18
PAGE 19
PAGE 20
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 21
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.