Datasheet

SN74ALVCH245

OCTAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES119D – JULY 1997 – REVISED MAY 1999

2–87

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D EPIC (Enhanced-Performance Implanted

CMOS) Submicron Process

D Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

D Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

D Package Options Include Plastic

Small-Outline (DW), Thin Very

Small-Outline (DGV), and Thin Shrink

Small-Outline (PW) Packages

description

This octal bus transceiver is designed for 1.65-V to 3.6-V V

operation.

The SN74ALVCH245 is designed for asynchronous communication between data buses. The device transmits

data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the

direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are

effectively isolated.

To ensure the high-impedance state during power up or power down, OE

should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH245 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OE DIR

OPERATION

L L B data to A bus

L H A data to B bus

H X Isolation

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC is a trademark of Texas Instruments Incorporated.

DGV, DW, OR PW PACKAGE

(TOP VIEW)

DIR

GND