Datasheet

SN74ALVC245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES271A APRIL 1999 REVISED MAY 1999
279
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Package Options Include Plastic
Small-Outline (DW), Thin Very
Small-Outline (DGV), and Thin Shrink
Small-Outline (PW) Packages
description
This octal bus transceiver is designed for 1.65-V
to 3.6-V V
CC
operation.
The SN74ALVC245 is designed for asynchronous
communication between data buses. The device
transmits data from the A bus to the B bus or from
the B bus to the A bus, depending on the logic level
at the direction-control (DIR) input. The
output-enable (OE
) input can be used to disable
the device so the buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OE
should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ALVC245 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE
INPUTS
OE DIR
OPERATION
L L B data to A bus
L H A data to B bus
H X Isolation
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC is a trademark of Texas Instruments Incorporated.
DGV, DW, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8