Datasheet
SN74HSTL162822
14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES091A – DECEMBER 1996 – REVISED APRIL 1997
7–7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus Family
D Inputs Meet JEDEC HSTL Standard
JESD8-6
D All Outputs Have Equivalent 25-Ω Series
Resistors
D Packaged in Plastic Thin Shrink
Small-Outline Package
description
This 14-bit to 28-bit D-type latch is designed for
3.15-V to 3.45-V V
CC
operation. HSTL levels are
expected on the inputs. LVTTL levels are driven
on the Q outputs.
All outputs are designed to sink up to 12 mA and
include 25-Ω series resistors to reduce overshoot
and undershoot.
The SN74HSTL162822 is particularly suitable for
driving an address bus to two banks of memory.
Each bank of 14 outputs is controlled with its own
latch-enable (LE
) input.
Each of the 14 data (D) inputs is tied to the inputs
of two D-type latches, which provide true data at
the outputs. While LE is low, the outputs (Q) of the
corresponding 14 latches follow the D inputs.
When LE
is taken high, the Q outputs are latched
at the levels set up at the D inputs.
The SN74HSTL162822 is characterized for
operation from –40°C to 90°C.
FUNCTION TABLE
INPUTS
OUTPUT
LE D
Q
L H H
L LL
H X Q
0
†
†
Output level before the
indicated steady-state input
conditions were established
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Widebus is a trademark of Texas Instruments Incorporated.
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1Q2
2Q1
1Q1
GND
D1
D2
D3
V
CC
D4
D5
D6
GND
D7
1LE
V
CC
V
REF
GND
GND
2LE
D8
GND
D9
D10
D11
V
CC
D12
D13
D14
GND
1Q14
2Q14
1Q13
2Q2
1Q3
GND
2Q3
1Q4
V
CC
2Q4
1Q5
GND
2Q5
1Q6
V
CC
2Q6
1Q7
GND
2Q7
2Q8
GND
1Q8
2Q9
V
CC
1Q9
2Q10
GND
1Q10
2Q11
V
CC
1Q11
2Q12
GND
1Q12
2Q13