Datasheet

SN74HSTL16918
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES096C – APRIL 1997 – REVISED JANUARY 1999
7–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
h
t
su
LOAD CIRCUIT
Data Input
V
REF
1.25 V
0.25 V
V
REF
V
REF
1.25 V
0.25 V
1.25 V
0.25 V
V
REF
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
V
REF
V
REF
1.25 V
0.25 V
V
OH
V
OL
Input
(see Note B)
Output
V
REF
From Output
Under Test
C
L
= 80 pF
(see Note A)
500 Ω
LE
NOTES: A. C
L
includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z
O
= 50 Ω, t
r
≤ 1 ns, t
f
≤ 1 ns.
C. The outputs are measured one at a time with one transition per measurement.
D. t
PHL
and t
PLH
are the same as t
pd
.
1.5 V 1.5 V
Figure 1. Load Circuit and Voltage Waveforms