Datasheet

SN74HSTL16918
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES096C – APRIL 1997 – REVISED JANUARY 1999
7–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus Family
D Inputs Meet JEDEC HSTL Std JESD 8-6 and
Outputs Meet Level III Specifications
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Packaged in Plastic Thin Shrink
Small-Outline Package
description
This 9-bit to 18-bit D-type latch is designed for
3.15-V to 3.45-V V
CC
operation. The D inputs
accept HSTL levels and the Q outputs provide
LVTTL levels.
The SN74HSTL16918 is particularly suitable for
driving an address bus to two banks of memory.
Each bank of nine outputs is controlled with its
own latch-enable (LE
) input.
Each of the nine D inputs is tied to the inputs of two
D-type latches that provide true data (Q) at the
outputs. While LE
is low, the Q outputs of the
corresponding nine latches follow the D inputs.
When LE
is taken high, the Q outputs are latched
at the levels set up at the D inputs.
The SN74HSTL16918 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUT
LE D
Q
L H H
L LL
H X Q
0
†
†
Output level before the
indicated steady-state input
conditions were established
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Widebus is a trademark of Texas Instruments Incorporated.
DGG PACKAGE
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2Q1
1Q1
GND
D1
D2
V
CC
D3
D4
GND
1LE
GND
V
REF
GND
2LE
GND
D5
D6
D7
V
CC
D8
D9
GND
2Q9
1Q9
V
CC
V
CC
1Q2
2Q2
GND
1Q3
2Q3
V
CC
1Q4
2Q4
GND
1Q5
2Q5
GND
1Q6
2Q6
V
CC
1Q7
2Q7
GND
1Q8
2Q8
V
CC
V
CC